參數(shù)資料
型號(hào)： TCM4400ETQFP
廠商： Texas Instruments, Inc.
英文描述： GSM/DCS BASEBAND AND VOICE A/D AND D/A RF INTERFACE CIRCUIT
中文描述： 的GSM / DCS的基帶和語音的A / D和D / A射頻接口電路
文件頁數(shù)： 46/64頁
文件大?。?/td> 888K
代理商： TCM4400ETQFP
TCM4400E
GSM/DCS BASEBAND AND VOICE A/D
AND D/A RF INTERFACE CIRCUIT
SLWS082A – JULY 1999 – REVISED MARCH 2000
46
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
baseband uplink data buffer
The baseband uplink data buffer is used to transmit the uplink burst data. The uplink data buffer contents are
shown in Table 8.
Table 8. Uplink Data Buffer
áááááááááááááááááááááááááááááááá
áááááááááááááááááááááááááááááááá
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áááááááááááááááááááááááááááá
áááááááááááááááááááááááááááá
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Bit 0
–
Bit 159 are the bits composing the sequence of the transmitted burst, bit 0 is transmitted first. For a normal
burst, the uplink data buffer is loaded as follows:
áááááááááááááááá
áááááááááááááááááá
BIT141
BIT142
BIT143
BIT144
BIT145
BIT146
BIT147
áááááááááááááááá
ááááááááááááááááááá
ááááááááá
BIT64
BIT45
BIT26
áááááááá
0
áááááá
áááááá
áááááá
áááááá
<–––ACCESS TYPE
BIT151
BIT152
BIT153
BIT154
BIT155
BIT156
BIT157
áááááááááááááááááááááááááááá
BIT41
BIT61
BIT65
BIT66
ááááááááááááá
BIT68
0
BIT32
BIT42
BIT46
BIT55
BIT38
BIT48
BIT39
0
áááááááááááááááááááááááááááá
BIT30
BIT51
BIT33
BIT34
BIT37
BIT58
BIT49
BIT69
0
0
1
0
0
0
BIT40
BIT60
BIT43
BIT62
BIT44
BIT47
0
BIT59
0
0
0
0
1
1
0
0
BIT50
BIT52
BIT53
BIT54
BIT56
BIT57
0
0
0
0
1
0
0
ááááááááá
BIT63
ááááááááááááááááááááá
BIT104
áááááá
BIT67
ááááááááá
W
W
W
0
ááááááááááá
BIT105
ááááááááááááá
ááááááááááá
áááááááááááááááá
BIT122
BIT132
BIT106
BIT107
BIT108
BIT109
0
0
0
1
0
0
BIT121
BIT131
BIT120
BIT140
BIT123
BIT124
BIT125
BIT126
BIT135
BIT127
BIT128
BIT129
BIT138
BIT139
0
BIT149
0
0
0
0
1
1
0
0
0
BIT130
BIT133
BIT134
BIT136
BIT137
BIT159
0
0
0
1
0
0
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BIT150
0
áááááááá
0
0
1
0
0
0
0
áááááááááááááááááááááááááááááá
Bit 0 to 3
: 4 guard bits
Bit 4 to 6
: 3 tail bits
Bit 7 to 66
: 58 data bits
Bit 67 to 92
: 26 training sequence bits
Bit 93 to 92
: 58 training sequence bits
Bit 151 to 153
: 3 tail bits
Bit 154 to 159
: 8 guard bits
At reset and after each transmission, the burst buffer is reinitialized with guard bits (all bits = 1). An address
pointer is incremented after each word written into the buffer so that next write operation affects the next word
of the buffer. This address pointer is set to the base address (Word 0) by a RESET, after transmission of a burst
or by setting the IBUFPTR bit to 1( this bit has to be set back to zero to release the address pointer).
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