參數(shù)資料
型號： TCM4400ETQFP
廠商： Texas Instruments, Inc.
英文描述： GSM/DCS BASEBAND AND VOICE A/D AND D/A RF INTERFACE CIRCUIT
中文描述： 的GSM / DCS的基帶和語音的A / D和D / A射頻接口電路
文件頁數(shù)： 5/64頁
文件大?。?/td> 888K
代理商： TCM4400ETQFP
TCM4400E
GSM/DCS BASEBAND AND VOICE A/D
AND D/A RF INTERFACE CIRCUIT
SLWS082A – JULY 1999 – REVISED MARCH 2000
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
QFP
BGA
ADCMID
44
H8
I/O
Reference voltage of auxiliary A/D converters; decoupling only (analog)
ADIN1
36
J7
I
Auxiliary 10-bit ADC input 1 (analog)
ADIN2
37
H7
I
Auxiliary 10-bit ADC input 2 (analog)
ADIN3
38
K8
I
Auxiliary 10-bit ADC input 5 (analog)
ADIN4
39
J8
I
Auxiliary 10-bit ADC input 4 (analog)
ADIN5
40
K9
I
Auxiliary 10-bit ADC input 3 (analog)
AFC
46
G9
O
Automatic frequency control DAC output (analog)
AGC
45
H10
O
Automatic gain control DAC output (analog)
APC
47
G10
O
Automatic power control DAC output (analog)
AUXI
29
K5
I
Auxiliary (high-level) speech signal input (analog)
AUXO
34
H6
O
Auxiliary downlink (voice codec) amplifier output, single-ended (analog)
AVDD1
AVDD2
AVDD3
AVDD4
AVDD5
AVSS1
AVSS2
AVSS3
AVSS4
BCAL
7
D1
Analog positive power supply (bandgap, internal common-mode generator, bias current generator).
56
D9
Analog positive power supply (baseband CODEC)
41
J9
Analog positive power supply (auxiliary RF functions)
30
J5
Analog positive power supply (voice codec)
43
H9
Analog positive power supply (output stages of auxiliary RF functions).
11
E3
Analog negative power supply (bandgap, internal common-mode generator, bias current generator).
55
D10
Analog negative power supply (baseband CODEC)
48
G8
Analog negative power supply (auxiliary RF functions)
31
H5
Analog negative power supply (voice codec)
72
A5
I
Baseband uplink or downlink offset calibration enable (timing interface)
BCLKR
5
C1
I/O
DSP serial interface clock input. This clock signal is provided by the DSP or the TCM4400E (digital/3-state).
BCLKX
2
B1
O
DSP serial interface clock output. The frequency is the same as MCLK (digital/3-state).
BDR
4
C3
I
DSP serial interface serial data input (digital)
BDX
3
C2
O
DSP serial interface serial data output (digital/3-state)
BENA
71
C6
I
Burst transmit or receive enable (depends on status of BULON and BDLON) (digital)
BDLON
74
C5
I
Power on of baseband downlink (timing interface)
BFSR
6
D2
I
DSP serial interface receive frame synchronization input (digital)
BFSX
1
B2
O
DSP serial interface transmit frame synchronization output (digital/3-state)
BDLIN
54
E8
I
In-phase baseband input (–) downlink path (analog)
BDLIP
53
E9
I
In-phase baseband input (+) downlink path (analog)
BDLQN
52
E10
I
Quadrature baseband input (–) downlink path (analog)
BDLQP
51
F8
I
Quadrature baseband input (+) downlink path (analog)
BULIN
59
C9
O
In-phase baseband output (–) uplink path (analog)
BULIP
60
B10
O
In-phase baseband output (+) uplink path (analog)
BULON
73
B5
I
Serial clock input (serial interface) (digital)
BULQN
57
D8
O
Negative quadrature baseband output. BULQN is an uplink path (analog)
BULQP
58
C10
O
Positive quadrature baseband output. BULQN is an uplink path (analog)
DVDD1
DVDD2
DVDD3
80
A2
Digital positive power supply (baseband and timing serial interfaces)
66
B7
Digital positive power supply (baseband CODEC)
42
J10
Digital positive power supply (auxiliary RF functions)
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