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參數(shù)資料
| 型號(hào)： | TC9324F |
| 廠商： | Toshiba Corporation |
| 英文描述： | Single-Chip DTS Microcontroller (DTS-20) |
| 中文描述： | 單芯片微丘（丘- 20） |
| 文件頁(yè)數(shù)： | 90/101頁(yè) |
| 文件大?。?/td> | 1831K |
| 代理商： | TC9324F |
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TC9324F
2002-02-08
90
Register Ports
The G-register, the data register, and the DAL address register mentioned in the CPU description are
treated as an internal port.
. G-Register (
φ
KL C,
φ
KL D)
This register addresses the row address (DR
=
04H to FFH) in data memory for the MVGD and MVGS
instructions. This register is accessed by the OUT1/IN1 instruction with the operand [CN
=
CH to DH].
Using the STGI instruction, data can be set in the register with just one instruction.
Note: The register value is only valid for the MVGD or MVGS instructions. The register is ignored for other
instructions. The MVGD and MVGS instructions have no effect on this register.
Note: Setting data 00H to FFH in the G-register allows all the data memory row addresses to be specified
indirectly. (DR
=
00H to FFH)
Note: This register can be both read and written. If necessary, at an interrupt, save and restore the register
contents using data memory.
G7
G6
G5
G4
G3
G2
G1
G0
DR
0
0
0
0
0
1
0
0
04H
0
0
0
0
0
1
0
1
05H
0
0
0
0
0
1
1
0
06H
1
1
1
1
1
1
1
0
FEH
1
1
1
1
1
1
1
1
FFH
φ
L/K1C
Y1
Y2
Y4
Y8
G0
G1
G2
G3
Data memory row address specification
φ
L/K1D
Y1
Y2
Y4
Y8
G4
G5
G6
G7
I
*
STGI instruction
Transfer
I0
I1
I2
I3
I4
I5
0
0
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