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參數(shù)資料
| 型號(hào)： | TC9324F |
| 廠商： | Toshiba Corporation |
| 英文描述： | Single-Chip DTS Microcontroller (DTS-20) |
| 中文描述： | 單芯片微丘（丘- 20） |
| 文件頁數(shù)： | 82/101頁 |
| 文件大?。?/td> | 1831K |
| 代理商： | TC9324F |
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TC9324F
2002-02-08
82
The A/D converter uses 8-bit resolution, successive comparison conversion. The internal power supply
(V
DD
) is used as the AD conversion reference voltage. The A/D converter compares the voltage resulting
from dividing the power supply by 256 with the A/D input voltage and outputs the comparison data to the
A/D conversion data port. The A/D conversion input is multiplexed to eight channels of external input pins
(pins ADIN1 to ADIN8) and selected by the AD SEL0 to SEL2 bits.
The A/D converter performs A/D conversion whenever the STA bit is set to 1. When the CPU clock is set
to 4.5 MHz, the CK SEL1/2 bits can select the conversion clock among 900-kHz, 100 kHz, and 50 kHz.
When the CPU clock is set to 75 kHz, the conversion clock is selected as 75 kHz. The corresponding
conversion times are: 23, 192, and 382
μ
s, and 294 μs. The BUSY bit can be referenced to check whether
A/D conversion is complete. After A/D conversion is complete, the controller loads the A/D conversion data
to data memory.
Use the following formula to calculate the A/D comparison result.
256
0.5
n
V
DD
×
(255
>
n
>
1)
<
A/D input voltage
<
256
0.5
n
V
DD
+
×
(254
>
n
>
0)
(where n is the [decimal] A/D conversion data value)
These control bits can be accessed by the OUT2 instruction with the operand [CN
=
0H, 1H] and the IN2
instruction with the operand [CN
=
0H to 2H] on I/O map page 3.
2. A/D Converter Circuit Structure
The A/D converter consists of a comparator, an A/D conversion latch, and a control circuit. Because the
comparator block operates only when the BUSY bit is set to 1, the A/D converter consumes no current when
not operating.
Note: Set to input ports the I/O ports corresponding to the A/D input pins used.
54
53
52
51
ADIN8 (P3-3)
Sample
and hold
ADIN7 (P3-2)
ADIN6 (P3-1)
ADIN5 (P3-0)
DCREF
Control
circuit
D
STA BUSY
A
BUSY
A
Comparator
SEL0~2
AD0
~
AD7
R
R
3
R
R
50
49
ADIN4 (P2-3)
ADIN3 (P2-2)
48
47
ADIN2 (P2-1)
ADIN1 (P2-0)
46 DCREF
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|---|---|
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