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參數(shù)資料
| 型號： | TC9324F |
| 廠商： | Toshiba Corporation |
| 英文描述： | Single-Chip DTS Microcontroller (DTS-20) |
| 中文描述： | 單芯片微丘（丘- 20） |
| 文件頁數(shù)： | 33/101頁 |
| 文件大?。?/td> | 1831K |
| 代理商： | TC9324F |
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TC9324F
2002-02-08
33
2. Wait Mode
Wait mode halts the system and maintains, with reduced current consumption, the internal state of the
system immediately prior to halting. Two Wait modes are supported: soft wait and hard wait. When the
Wait instruction is executed, execution halts at the address of the WAIT instruction. Therefore, when Wait
mode is released, execution starts again from the next address (without delaying for the standby time).
(1)
Soft Wait Mode
Executing the WAIT instruction with the operand [P
=
0H] stops the device’s internal CPU only. In
this mode, the crystal oscillator and other circuitry continue to operate normally. Using Soft Wait
mode in the software for clock functions reduces the current consumed during clock operation.
Note: The current consumption varies according to the software because the current consumed is
dependent on the time for executing CPU operations.
(2)
Hard Wait Mode
Executing a WAIT instruction with the operand [P
=
1H] stops all operation other than the crystal
oscillator. This reduces current consumption still further than Soft Wait mode. In this state, CPU
operation is halted.
Note: During Hard Wait mode, the output ports are retained and the LCD output pins are all fixed to L.
(3)
Setting Wait Mode
Executing the WAIT instruction always sets Wait mode.
Note: In Wait mode, the PLL is automatically turned off.
(4)
Wait Mode Release Conditions
Wait mode is released by the following conditions.
1)
At a change in the input state of the HOLD pin.
2)
At a change in the input state of an I/O port (P8-0 to 3) set as an input port.
3)
When the 2-Hz timer F/F is set to 1. (In Soft Wait mode only)
3.
HOLD
Input Port
The HOLD pin can be used as an input port. Executing the IN2 instruction with the operand [CN
=
8H]
reads the data input from this bit to data memory.
When setting Clock Stop or Wait mode, always access this port prior to executing the backup instruction.
Note that if the instruction is executed without first accessing this port, the device may not enter Clock
Stop or Wait mode.
When the HOLD PLL off control bit is set to 1, inputting L level to the HOLD pin sets PLL Off mode.
PLL OFF mode can be quickly set when changing the batteries. This bit is accessed by the OUT1
instruction with the operand [CN
=
9H] on I/O map page 2. PLL Off mode can also be set by setting all the
reference ports to 1. (See the section on the reference frequency divider.)
0: Input L level
1: Input H level
Y1
Y2
Y4
Y8
φ
K28
HOLD
0: No PLL off control by the
HOLD
pin
1: PLL set to Off mode by
HOLD
pin (L level input)
Y1
Y2
Y4
Y8
φ
L19P2
HOLD
PLL off
control
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