參數(shù)資料
型號(hào)： TC9324F
廠商： Toshiba Corporation
英文描述： Single-Chip DTS Microcontroller (DTS-20)
中文描述： 單芯片微丘（丘- 20）
文件頁數(shù)： 34/101頁
文件大?。?/td> 1831K
代理商： TC9324F
TC9324F
2002-02-08
34
Interrupt Function
Peripheral hardware that can use interrupts is the INTR1 and INTR2 pins, serial interfaces 1 to 4, and
the timer-counter.
When the peripheral hardware satisfies the conditions, the hardware outputs an interrupt request signal
and issues an interrupt request. When the interrupt is accepted, processing branches to the vector address
determined by the interrupt source and the interrupt handling routine commences.
At the start and end of normal interrupt handling in an interrupt routine, prior processing and post
processing are needed to restore the state that prevailed when the interrupt occurred. The registers used
by the ALU and any data memory that was not corrupted must be saved and restored to the interrupt data
memory. When the interrupt handling is complete, the program is restored by an interrupt return
instruction.
. Interrupt Control Circuit
The interrupt control circuit consists of an interrupt enable flag, an interrupt latch, and an interrupt
priority circuit block. These are controlled and set by the OUT1/IN1 instructions on page 2 of the I/O map.
(1)
Interrupt Enable Flag
The interrupt enable flags include the master enable flag and individual enable flags for each
interrupt source. The individual enable flags enable or disable interrupts in accordance with the
interrupt source. The master enable flag can enable or disable any interrupt. Setting the enable
register to 1 enables an interrupt while 0 disables the interrupt.
The individual enable flags are accessed by the OUT1/IN1 instruction with the operand [CN
=
1H,
2H] on I/O map page 2.
The master enable flag enables/disables an interrupt on execution of the EI/DI instruction. To
disable an interrupt during program execution use the DI instruction. To enable an interrupt, use the
EI instruction. Interrupts are enabled while the program between the EI and DI instructions is
executing.
The master enable flag is reset to 0 when an interrupt request is received and all interrupts are
disabled. An interrupt return instruction sets the flag to 1. The master enable flag can be read by the
IN1 instruction with the operand [CN
=
0H] on I/O map page 2 to data memory.
Y1
Y2
Y4
Y8
φ
K11P2
EF1
EF2
EF3
EF4
EF1
INTR1 pin
EF2
INTR2 pin
EF3
Serial interface 3/4
EF4
Serial interface 1
EF5
8-bit timer-counter
EF6
Serial interface 2
Individual enable flag
“0”
Disabled
“1”
Enabled
Reset to 0 when an interrupt is accepted or when a DI
instruction is executed.
Set to 1 when an interrupt return or EI instruction is executed.
Y1
Y2
Y4
Y8
φ
K10P2
MF
Master enable flag
Y1
Y2
Y4
Y8
φ
L11P2
EF1
EF2
EF3
EF4
Y1
Y2
Y4
Y8
φ
K12P2
EF5
EF6
0
0
Y1
Y2
Y4
Y8
φ
L12P2
EF5
EF6
*
*
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