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參數(shù)資料
| 型號： | TC9324F |
| 廠商： | Toshiba Corporation |
| 英文描述： | Single-Chip DTS Microcontroller (DTS-20) |
| 中文描述： | 單芯片微丘（丘- 20） |
| 文件頁數(shù)： | 43/101頁 |
| 文件大?。?/td> | 1831K |
| 代理商： | TC9324F |
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TC9324F
2002-02-08
43
Programmable Counter
The programmable counter block consists of a 2-modulus prescaler, 4-bit and 13-bit programmable
counters, and the ports used to control the block.
The programmable counters can be turned on and off by the contents of the reference ports or the
HOLD input state.
. Programmable Counter Control Ports
These ports control the frequency, division method, and the prescaler operating current and gain.
The division method and the prescaler power control are accessed using the OUT1 instruction with the
operand [CN
=
0H] on I/O map page 1.
The frequency is accessed using the OUT1 instruction with the operand [CN
=
1 to 5H] on I/O map page
1. The frequency is set by writing to bit P16 (
φ
L15P1). When the programmable counter data (P16) are set,
all the data from P0 to P16 are updated. Therefore, always access P16 and set it last, even when changing
only a portion of the data.
Setting the prescaler IF input: When this bit (Y8) is set to 1 the programmable counter is halted and the
prescaler 1/1516 is fixed to 1/16. Normally when setting a PLL, set 0 to the bit. (See the section on the IF
counter.)
Y1
Y2
Y4
Y8
φ
L10P1
HF
PW
*
FM
Division method setting
Power control
Programmable counter frequency setting
φ
L11P1
Y1
Y2
Y4
Y8
P0
P1
P2
P3
φ
L12P1
Y1
Y2
Y4
Y8
P4
P5
P6
P7
φ
L13P1
Y1
Y2
Y4
Y8
P8
P9
P10 P11
φ
L14P1
Y1
Y2
Y4
Y8
P12 P13 P14 P15
φ
L15P1
Y1
Y2
Y4
Y8
P16
*
*
*
LSB
MSB
Y1
Y2
Y4
Y8
φ
L19P2
Prescaller
IN
0: Proper PLL structure
1: Inputs the prescaler divider output to the IF counter.
Sets the prescaler IF counter input.
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