
TC9324F
2002-02-08
31
Backup Modes
To access the three Backup modes, execute the CKSTP or WAIT instruction.
. Clock Stop Mode
Clock Stop mode halts the system and maintains the internal state of the system immediately prior to
halting at low current consumption (1
μ
A or below). In Clock Stop mode, the crystal oscillator halts and the
LCD display output pins and CMOS output ports are all automatically fixed to the L level. The supply
voltage can be reduced to 2.0 V.
When the CKSTP instruction is executed, execution halts at the address of the CKSTP instruction.
Therefore, execution starts again from the next address when Clock Stop mode is released (after a standby
period of around 100ms).
(1)
Setting Clock Stop Mode
Clock Stop mode can be set to one of two modes. The CKSTP MODE bit determines which of the
two modes are set. This bit is accessed by the OUT1 instruction with the operand [CN
=
8H] on I/O
map page 2.
1)
MODE-0
In mode 0, executing the CKSTP instruction when the HOLD pin is L sets Clock Stop mode.
Executing the CKSTP instruction when the HOLD pin is H is equivalent to executing a NOOP
instruction.
2)
MODE-1
In mode 1, executing the Clock Stop instruction sets Clock Stop mode regardless of the level of
the HOLD pin.
Note: The PLL is off during execution of the CKSTP instruction.
Note: Prior to executing the CKSTP instruction, be sure to access the HOLD input and I/O port 8 input
ports to reset the 2-Hz F/F. Attempting to set Clock Stop mode without resetting the 2-Hz F/F may
result in a failure to set the mode.
(2)
Releasing Clock Stop Mode
1)
MODE-0
In mode 0, Clock Stop mode is released when the HOLD pin goes to H, or by a change in the
input state of any I/O port (P8-0 to 3) pin set to input mode.
2)
MODE-1
In mode 1, Clock Stop mode is released by a change in the input state of the HOLD pin or of
any I/O port (P8-0 to 3) pin set to input mode.
Y1
Y2
Y4
Y8
φ
L18P2
CKSTP
mode
0: MODE-0
1: MODE-1