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參數(shù)資料
| 型號： | TC9324F |
| 廠商： | Toshiba Corporation |
| 英文描述： | Single-Chip DTS Microcontroller (DTS-20) |
| 中文描述： | 單芯片微丘（丘- 20） |
| 文件頁數(shù)： | 47/101頁 |
| 文件大?。?/td> | 1831K |
| 代理商： | TC9324F |
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TC9324F
2002-02-08
47
Phase Comparator, Lock Detection Port
The phase comparator compares the reference frequency supplied by the reference frequency divider with
the output frequency of the programmable counter, and outputs the phase difference. This is used to control
the VCO (voltage control oscillator) via the low pass filter so as to match the frequencies and phases
between the two signals.
The phase comparator outputs in parallel to the tristate buffered DO1 and DO2 pins. This enables the
optimal filter constants to be designed for FM, VHF, and AM bands.
Also, the DO2 pin can be set as a general-purpose output by the DO2 control port. By using the DO1 and
DO2 pins, the PLL lock loop lockup time characteristics can be improved.
The unlock detection port can be used to detect the PLL lock state.
. DO Control Port, Unlock Detection Port
The M0 and M1 bits of the DO2 control port set DO2 as a general-purpose output port and set DO2 to
high impedance. The FAST bit sets the high-speed lock.
The unlock F/F detects the phase difference between the output frequency of the programmable counter
and the reference frequency when the phase is approximately 180°. If the phase does not match, that is, if
the PLL is unlocked, the unlock F/F is set. Also, setting the unlock reset bit to 1 resets the unlock F/F.
To detect the phase difference at the reference frequency period, reset the unlock F/F, then access the
unlock F/F after waiting for an interval longer than the reference frequency period. An enable bit is
supplied for this purpose. After confirming that the unlock enable bit is set to 1, access the unlock F/F.
Note: When the PLL is off and the DO output is set, the DO output is high impedance. However, when the DO2
pin outputs an L or H level signal, this state is held if PLL Off mode or Clock Stop mode is set.
Note: The high-speed lock is effective only when a 4.5-MHz peripheral clock is selected.
Y1
Y2
Y4
Y8
DO2 control
φ
L1AP1
UNLOCK
RESET
FAST
M0
M1
Set DO2 output
Set high-speed
lock
Setting 1 resets the unlock F/F and unlock enable bit.
Y1
Y2
Y4
Y8
UNLOCK
F/F
φ
K2A
ENA
Unlock enable
0: Waiting for PLL unlock detection
1: PLL unlock detectable
0: PLL locked
1: PLL unlocked
Unlock detection bit
FAST
M1
M0
DO2 output state
DO1 output state
0
0
0
DO output
0
0
1
L level
0
1
0
H level
0
1
1
“HZ”
DO output
1
*
*
When phase difference 1.11 μs
or higher: DO output
When phase difference less
than 1.11 μs: “HZ”
DO output
Valid only when 4.5 MHz
selected as the peripheral
clock
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