
www.ti.com
SLES197C – APRIL 2007 – REVISED MARCH 2011
3.2
SAP Clock Management
The Serial Audio Port in the TAS3204 can be clocked in two modes of operation: Master and Slave. By
default, the TAS3204 is configured in master mode.
Clock Master operation: In Clock Master operation, the onboard oscillator provides the reference for the
SAP clock outputs provided an external crystal is present.
LRCLK_OUT fixed at a frequency of 48 kHz (Fs).
SCLK_OUT is fixed at a frequency of (64 x Fs).
MCLK_OUT is fixed at a frequency of (256 x Fs).
In master mode, the external ASRC converts incoming serial audio data to 48-kHz sample rate
synchronous to the internally generated serial audio data clocks.
Clock Slave operation: In Clock Slave operation, the SAP clock inputs are provided externally (that is, by
a system controller) and passed through to the SAP Outputs.The MCLK_IN signal is internally divided
down and sent directly to the ADC and DAC blocks, therefore analog audio performace is dependant on
the quality of the MCLK_IN signal. As a result, degradation in analog performance is to be expected if the
quality of MCLK_IN (that is, jitter, phase noise, etc) is not robust.
DISCLAIMER: Analog performance is not ensured in slave mode, as the analog performance depends
upon the quality of the MCLK_IN. The TAS3204 is not robust with respect to MCLK_IN errors (glitches,
etc.); if the MCLK_IN frequency changes under operation, the device must be reset.
MCLK_IN (512 × Fs),
SCLK_IN (64 × Fs), and
LRCLK_IN (Fs) are supplied externally by an clocking device.
When the TAS3204 is used in a system in which the master clock frequency (fMCLK ) can change, the
TAS3204 must be reset during the frequency change. In these cases, the procedure shown in
Figure 3-2should be used.
In slave mode, all incoming serial audio data must be synchronous to an incoming LRCLK_IN of 44.1 kHz
or 48 kHz.
The TAS3204 only supports dynamic sample-rate changes between any of the supported sample
frequencies when a fixed-frequency master clock is provided. During dynamic sample-rate changes, the
TAS3204 remains in normal operation and the register contents are preserved. To avoid producing audio
artifacts during the sample-rate changes, a volume or mute control can be included in the application
firmware that mutes the output signal during the sample-rate change. The fixed-frequency clock can be
provided by a crystal attached to XTAL_IN and XTAL_OUT or an external 3.3-V fixed-frequency TTL
source attached to MCLK_IN.
Changing the sample rate on the fly in slave mode should be handled by a host system controller. The
TAS3204 does not include any internal clock error or click/pop detection managment. Customer specific
DAP filter coefficients must be uploaded by a host system controller when changing the sample rate.
Copyright 2007–2011, Texas Instruments Incorporated
TAS3204 Clocking System
9