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參數(shù)資料
| 型號(hào)： | TAS3204PAG |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | GREEN, PLASTIC, TQFP-64 |
| 文件頁數(shù)： | 56/76頁 |
| 文件大?。?/td> | 1224K |
| 代理商： | TAS3204PAG |
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SLES197C – APRIL 2007 – REVISED MARCH 2011
www.ti.com
2.2
Terminal Descriptions
TERMINAL
INPUT/
PULLUP/
DESCRIPTION
OUTPUT(1)
PULLDOWN(2)
NAME
NO.
AIN1LM
13
Analog Input
Pull to VMID(3)
Analog channel 1 left negative input
AIN1LP
12
Analog Input
Analog channel 1 left positive input
AIN1RM
15
Analog Input
Pull to VMID(3)
Analog channel 1right negative input
AIN1RP
14
Analog Input
Analog channel 1 right positive input
AIN2LM
17
Analog Input
Pull to VMID(3)
Analog channel 2 left negative input
AIN2LP
16
Analog Input
Analog channel 2 left positive input
AIN2RM
19
Analog Input
Pull to VMID(3)
Analog channel 2 right negative input
AIN2RP
18
Analog Input
Analog channel 2 right positive input
AIN3LM
21
Analog Input
Pull to VMID(3)
Analog channel 3 left negative input
AIN3LP
20
Analog Input
Analog channel 3 left positive input
AIN3RM
23
Analog Input
Pull to VMID(3)
Analog channel 3 right negative input
AIN3RP
22
Analog Input
Analog channel 3 right positive input
AOUT1LM
33
Analog Output
Analog channel 1 left negative output
AOUT1LP
34
Analog Output
Analog channel 1 left positive output
AOUT1RM
35
Analog Output
Analog channel 1 right negative output
AOUT1RP
36
Analog Output
Analog channel 1 right positive output
AOUT2LM
29
Analog Output
Analog channel 2 left negative output
AOUT2LP
30
Analog Output
Analog channel 2 left positive output
AOUT2RM
31
Analog Output
Analog channel 2 right negative output
AOUT2RP
32
Analog Output
Analog channel 2 right positive output
3.3-V analog power. This pin must be decoupled according to good
AVDBit 1
24
Power
design practices.
AVSS1
11
Power
Analog ground
3.3-V analog power. This pin must be decoupled according to good
AVDBit 2
28
Power
design practices.
AVSS2
37
Power
Analog ground
3.3-V analog power supply. This pin must be decoupled according to
AVDBit 3
40
Power
good design practices.
AVSS3
38
Power
Analog ground
CS0
6
Digital Input
I2C chip select
3.3-V digital power. This pin must be decoupled according to good
DVDBit 1
9
Power
design practices.
DVSS1
8
Power
Digital ground
3.3-V digital power. This pin must be decoupled according to good
DVDBit 2
45
Power
design practices.
DVSS2
44
Power
Digital ground
3.3-V digital power. This pin must be decoupled according to good
DVDBit 3
57
Power
design practices.
DVSS3
56
Power
Digital ground
GPIO1
4
Digital IO
General purpose input/output pin #1.
GPIO2
3
Digital IO
General purpose input/output pin #2
I2C1_SCL
1
Digital Input
Slave I2C serial control data interface input/output.
I2C1_SDA
2
Digital I/O
Slave I2C serial clock input.
I2C2_SCL
64
Digital Input
Master I2C serial control data interface input/output.
(1)
I = input; O = output
(2)
All pullups are 20-
μA weak pullups, and all pulldowns are 20-μA weak pulldowns. The pullups and pulldowns are included to ensure
proper input logic levels if the terminals are left unconnected (pullups
→ logic 1 input; pulldowns → logic 0 input). Devices that drive
inputs with pullups must be able to sink 20
μA while maintaining a logic-0 drive level. Devices that drive inputs with pulldowns must be
able to source 20
μA while maintaining a logic-1 drive level.
(3)
Pull to VMID when analog input is in single-ended mode.
6
Physical Characteristics
Copyright 2007–2011, Texas Instruments Incorporated
Product Folder Link(s): TAS3204
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