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參數(shù)資料
| 型號： | TAS3204PAG |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | GREEN, PLASTIC, TQFP-64 |
| 文件頁數(shù)： | 62/76頁 |
| 文件大?。?/td> | 1224K |
| 代理商： | TAS3204PAG |
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www.ti.com
SLES197C – APRIL 2007 – REVISED MARCH 2011
Table 12-24. Digital Cross Bar (0x30 to 0x3F) (continued)
REGISTER
SUBADDRESS
NO. OF BYTES
CONTENTS
INITIALIZATION VALUE
NAME
0x00 00 00 00
0x3D
CH6 Output Mixer
32
Input cross bar mux
0x00 00 00 00
0x08 00 00 00
0x00 00 00 00
0x3E
CH7 Output Mixer
32
Input cross bar mux
0x00 00 00 00
0x08 00 00 00
0x00 00 00 00
0x3F
CH8 Output Mixer
32
Input cross bar mux
0x00 00 00 00
0x08 00 00 00
12.16 Extended Special Function Registers (ESFR) Map
ESFR provide communication between the embedded MCU and the DSP core. The following table
outlines the functionality of the ESFRs. These registers should only be accessed if the user intend to write
custom TAS3204 MCU Program Code as changing some of these registers may result in undesired or
unspecified operation of the TAS3204 DAP.
Table 12-25. Extended Special Fucntion Registers (ESFR)
ESFR
MAPPED_TO
NO. OF
DIRECTION
CONNECTING
REGISTER TYPE
DESCRIPTION
BITS
BLOCK
8-bit asynchronous rstz
di_o
8
OUT
positive edge triggered
I2C
Data to be transferred from MCU to I2C
Reset low
Data to be transferred from I2C to MCU
85
da_i
8
IN
NO REG - direct input
I2C
during slave write in I2C slave-write mode if
the MCU controls I2C interface
Indicates the type of information being
relayed to the MCU. This affects how the
86
sub_addr_i
8
IN
NO REG – direct input
I2C
MCU changes the data that follows the
subaddress.
91
data_out1_i
8
IN
NO REG – direct input
I2C
92
data_out2_i
8
IN
NO REG – direct input
I2C
These registers are used to deliver data
from the I2C block to the MCU.
93
data_out3_i
8
IN
NO REG – direct input
I2C
94
data_out4_i
8
IN
NO REG – direct input
I2C
8-bit asynchronous rstz
Address of I2C internal registers. See Mentor
95
A_o
3
OUT
positive edge triggered
I2C
I2C product specification.
Reset Low
8-bit asynchronous rstz
Bit definition follows functional spec
96
i2s_word_byte_t
8
OUT
SAP
positive edge triggered
definition for specification SAP WORD byte
Reset Low
8-bit asynchronous rstz
Bit definition follows functional spec
97
i2s_mode_byte_t
8
OUT
SAP
positive edge triggered
definition for specification SAP mode byte
Reset Low
5-bit asynchronous rstz
Bit definition follows functional spec
A1
MLRCLK_t
5
OUT
CLOCK
positive edge triggered
definition for specification MLRCLK field
Reset Low
Copyright 2007–2011, Texas Instruments Incorporated
65
I2C Register Map
Product Folder Link(s): TAS3204
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