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| 型號(hào)： | TAS3204PAG |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類(lèi)： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | GREEN, PLASTIC, TQFP-64 |
| 文件頁(yè)數(shù)： | 38/76頁(yè) |
| 文件大?。?/td> | 1224K |
| 代理商： | TAS3204PAG |
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XTALI
MCLKO
MCLKI
tw(MCLKI)
tf(MCLKO)
tc(1)
tc(2)
tc(3)
tw(MCLKO)
tr(MCLKO)
td(MI-MO)
T0088-01
www.ti.com
SLES197C – APRIL 2007 – REVISED MARCH 2011
11.6 Timing Characteristics
The following sections describe the timing characteristics of the TAS3204.
11.7
Master Clock
over recommended operating conditions (unless otherwise noted)
TEST
PARAMETER
MIN
TYP
MAX
UNIT
CONDITIONS
f(XTAL_IN)
Frequency, XTAL_IN (1/ tc(1))
See (1)
512Fs
Hz
tc(1)
Cycle time, XTAL_IN
1÷512Fs
Sec
f(MCLK_IN)
Frequency, MCLK_IN (1/ tc(2))
512Fs
Hz
tw(MCLK_IN)
Pulse duration, MCLK_IN high
See (2)
0.4 tc(2)
0.5 tc(2)
0.6 tc(2)
ns
Crystal frequency deviation
50
ppm
f(MCLKO)
Frequency, MCLKO (1/ tc(3))
256Fs
Hz
tr(MCLKO)
Rise time, MCLKO
CL = 30 pF
15
ns
tf(MCLKO)
Fall time, MCLKO
CL = 30 pF
15
ns
tw(MCLK_IN)
Pulse duration, MCLKO high
See (3)
HMCLKO
ns
XTAL_IN master clock
80
ps
source
MCLKO jitter
MCLK_IN master clock
See (4)
ps
source
MCLKO = MCLK_IN
See (5)
20
ns
Delay time, MCLK_IN rising
td(MI-MO)
edge to MCLKO rising edge
MCLKO < MCLK_IN
See (5) (6)
20
ns
(1)
Duty cycle is 50/50.
(2)
Period of MCLK_IN = TMCLK_IN = 1/fMCLK_IN
(3)
HMCLKO = 1/(2 × MCLKO). MCLKO has the same duty cycle as MCLK_IN when MCLKO = MCLK_IN. When MCLKO = 0.5 MCLK_IN or
0.25 MCLK_IN, the duty cycle of MCLKO is typically 50%.
(4)
When MCLKO is derived from MCLK_IN, MCLKO jitter = MCLK_IN jitter
(5)
Only applies when MCLK_IN is selected as master source clock
(6)
Also applies to MCLKO falling edge when MCLKO = MCLK_IN/2 or MCLK_IN/4
Figure 11-3. Master Clock Signal Timing Waveforms
Copyright 2007–2011, Texas Instruments Incorporated
Electrical Specifications
43
Product Folder Link(s): TAS3204
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