參數(shù)資料
型號(hào)： TAS3204PAG
廠商： TEXAS INSTRUMENTS INC
元件分類(lèi)： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP64
封裝： GREEN, PLASTIC, TQFP-64
文件頁(yè)數(shù)： 48/76頁(yè)
文件大?。?/td> 1224K
代理商： TAS3204PAG
SLES197C – APRIL 2007 – REVISED MARCH 2011
www.ti.com
12.4 I
2C Memory Load Control and Data Registers (0x04 and 0x05)
Registers 0x04 (Table 12-4) and 0x05 (Table 12-5) allow the user to download TAS3204 program code
and data directly from the system I2C controller.
The I2C slave memory load port permits the system controller to load the TAS3204 memories as an
alternative to having the TAS3204 load its memory from EEPROM.
MCU program memory
MCU extended memory
DAP program memory
DAP coefficient memory
DAP data memory
The transfer is performed by writing to two I2C registers. The first register is a eight byte register that holds
the checksum, the memory to be written, the starting address, the number of data bytes to be transferred.
The second location holds 8 bytes of data. The memory load operation starts with the first register being
set. Then the data is written into the second register using the format shown. After the last data byte is
written into the second register, an additional two bytes are written which contain the two-byte checksum.
At that point, the transfer is complete and status of the operation is reported in the status register. The end
checksum is always contained in the last two bytes of the data block.
Table 12-4. TAS3204 Memory Load Control Register (0x04)
BYTE
DATA BLOCK FORMAT
SIZE
NOTES
Checksum of bytes 2 through N + 8. If this is a termination header,
1-2
Checksum code
2 bytes
this value is 00 00.
0: MCU program memory
1: MCU external data memory
2: Audio DSP core program memory
3: Audio DSP core coefficient memory
3
Memory to be loaded
1 byte
4: Audio DSP core data memory
5: Audio DSP core upper data memory
6: Audio DSP core upper coefficient memory
7–15: Reserved for future expansion
4
Unused
1 byte
Reserved for future expansion
5–6
Starting TAS3204 memory address
2 bytes
If this is a termination header, this value is 0000.
7–8
Number of data bytes to be transferred
2 bytes
If this is a termination header, this value is 0000.
Table 12-5. TAS3204 Memory Load Data Register (0x05)
BYTE
8-BIT DATA
28-BIT DATA
48-BIT DATA
54-BIT DATA
1
Datum 1 Bit 7–Bit 0
0000 Bit 27–Bit 24
0000 0000
2
Datum 2 Bit 7–Bit 0
Bit 7–Bit 0
0000 0000
00 Bit 53–Bit 48
3
Datum 3 Bit 7–Bit 0
Bit 15–D8
Bit 47–Bit 40
4
Datum 4 Bit 7–Bit 0
Bit 7–Bit 0
Bit 39–Bit 32
5
Datum 5 Bit 7–Bit 0
0000 Bit 27–Bit 24
Bit 31–Bit 24
6
Datum 6 Bit 7–Bit 0
Bit 23–Bit 16
7
Datum 7 Bit 7–Bit 0
Bit 15–D8
8
Datum 8 Bit 7–Bit 0
Bit 7–Bit 0
52
Copyright 2007–2011, Texas Instruments Incorporated
I2C Register Map
Product Folder Link(s): TAS3204
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