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SLES197C – APRIL 2007 – REVISED MARCH 2011
9
TAS3204 Control Pins
9.1
Reset (RESET) - Power-Up Sequence
The RESET pin is an asynchronous control signal that restores all TAS3204 components to the default
configuration. When a reset occurs, the audio DSP core is put into an idle state and the 8051 starts
initialization. A valid XTAL_IN must be present when clearing the RESET pin to initiate a device reset. A
reset can be initiated by applying a logic 0 on RESET.
As long as RESET is held LOW, the device is in the reset state. During reset, all I2C and serial data bus
operations are ignored. The I2C interface SCL and SDA lines go into a high-impedance state and remain
in that state until device initialization has completed.
The rising edge of the reset pulse begins the initialization housekeeping functions of clearing memory and
setting the default register values. Once these are complete, the TAS3204 enables its master I2C interface
and disables its slave I2C interface and startes the boot sequence.
Using the master interface, the TAS3204 automatically tests to see if an external I2C EEPROM is at
address "1010x". The value x can be chip selects, other information, or don't care, depending on the
EEPROM selected.
If a memory is present and it contains the correct header information and one or more blocks of
program/memory data, the TAS3204 begins to load the program, coefficient and/or data memories from
the external EEPROM. The download is considered complete when an end of program header is read by
the TAS3204. At this point, the TAS3204 disables the master I2C interface, enable the slave I2C interface,
and start normal operation. After a successful download, the MCU program counter is reset, and the
downloaded MCU and DAP application firmware controls execution.
If no external EEPROM is present or if an error occurs during the EEPROM read, TAS3204 disables the
master I2C interface and enables the slave I2C interface initialization to load the slave default
configuration. In this default configuration, the TAS3204 streams audio from input to output if GPIO1 is
asserted LOW; if the GPIO1 pin is asserted HIGH, the ADC and the DAC are muted.
On power up, it is recommended that the TAS3204 RESET be held LOW until DVDD has reached 3.3 V.
This can be done by programming the system controller or by using an external RC delay circuit. The
1-k
and 1-μF values provide a delay of approximately 200 μs. The values of R and C can be adjusted to
provide other delay values as necessary.
Note: The master and slave interfaces do not operate simultaneously.
9.2
Voltage Regulator Enable (VREG_EN)
Setting the VREG_EN high shuts down all voltage regulators in the device. Internal register settings are
lost in this power down mode. A full power-up/reset/program-load sequence must be completed before the
device is operational.
9.3
Power Down (PDN)
The TAS3204 supports a number of power-down modes.
PDN can be used to put the device into power saving standby mode. PDN is user-firmware definable. Its
default configuration is to stop all clocks, power down all analog circuitry, and ramp down volume for all
digital inputs. This mode is used to minimize power consumption while preserving register settings. If there
is no EEPROM or if the EEPROM has an invalid image–i.e., an unsuccessful boot from the EEPROM–and
PDN is pulled low, the TAS3204 is in powerdown mode. After a successful boot, PDN is defined by the
boot code.
Individual power down DAC and ADC – Each stereo DAC and ADC can be powered down individually. To
avoid audible artifacts at the outputs, the sequences defined in the TI document TAS3108/TAS3108IA
Firmware Programmer's Guide (
SLEU067) must be followed. The control signals for these operations are
defined as ESFR. The feature is made available to the board controller via the I2C interface.
Copyright 2007–2011, Texas Instruments Incorporated
TAS3204 Control Pins
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