參數(shù)資料
型號： T7264
英文描述： T7264 U-Interface 2B1Q Transceiver
中文描述： T7264 U型接口2B1Q收發(fā)器
文件頁數(shù)： 6/54頁
文件大?。?/td> 876K
代理商： T7264
6
Lucent Technologies Inc.
Data Sheet
April 1998
T7264 U-Interface 2B1Q Transceiver
Pin Information
(continued)
Table 3. Clock Configuration
* The 10.24 MHz CKOUT is high for one-half of a 15.36 MHz period and low for one 15.36 MHz period. To compensate for the difference be-
tween the phase-locked and free-run frequencies, one-half 15.36 MHz clock periods are occasionally either removed from or added to the low
time of the 10.24 MHz period.
Functional Overview
5-5162F
Figure 3. Quat Example
V
DDO
+5 V
+5 V
+5 V
+5 V
0 V
0 V
MCLK
0
0
1
1
15.36 MHz
15.36 MHz
CKSEL
0
1
0
1
0
1
CKOUT
*
15.36 MHz (free-running)
10.24 MHz (phase-locked)
7.68 MHz (free-running)
3-stated (default)
15.36 MHz (free-running)
3-stated
–1
01
+3
10
+1
11
–3
00
–3
00
+1
11
+3
10
–3
00
–1
01
–1
01
+1
11
–1
01
–3
00
+3
10
+3
10
–1
01
+1
11
+3
+1
–1
–3
QUAT
BITS
The T7264 chip conforms to the T1.601 ANSI North
American 1992 Standard for 2B1Q line encoding. The
2B1Q line code provides a four-level pulse amplitude
modulation code with no redundancy. Data is grouped
into pairs of bits for conversion to quaternary (quat)
symbols. Figure 3 above shows an example of this cod-
ing method.
The analog front end provides the 2B1Q line coder
(D/A conversion), pulse shaper, line driver, first-order
line balance network, crystal oscillator clock genera-
tion, and sigma-delta A/D conversion. The line driver
provides pulses which allow the 2.5 V template of the
T1.601 specification to be met when connected to the
proper transformer and interface circuitry. The A/D con-
verter is implemented using a double-loop, sigma-delta
modulator.
A crystal oscillator provides the 15.36 MHz master
clock for the chip. An on-chip, digital phase-locked loop
provides the ability to synchronize the chip clock to the
system clock in the LT or to the line clock in the NT.
Provisions are made for using either an on-chip crystal
oscillator with an external crystal, or using an external
clock source.
The T7264 takes input at the K2 interface and formats
this information for the U-interface through a scram-
bling algorithm and the addition of synchronization bits
for U framing. This data is then transferred to the 2B1Q
encoder for transmission over the U loop. Signals com-
ing from the U loop are first passed through the sigma-
delta A/D converter and then sent for extensive signal
processing. The T7264 provides decimation of the
sigma-delta output (DEC), linear and nonlinear echo
cancellation, automatic gain control (AGC), signal
detection, decision feedback equalization (DFE), timing
recovery (TR), descrambling, line-code polarity detec-
tion, and rate adaption for output onto the K2 interface.
The DFE circuit provides the functionality necessary for
proper operation on subscriber loops with bridged taps.
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