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參數(shù)資料
| 型號： | T7264 |
| 英文描述： | T7264 U-Interface 2B1Q Transceiver |
| 中文描述： | T7264 U型接口2B1Q收發(fā)器 |
| 文件頁數(shù)： | 46/54頁 |
| 文件大?。?/td> | 876K |
| 代理商： | T7264 |
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46
Lucent Technologies Inc.
Data Sheet
April 1998
T7264 U-Interface 2B1Q Transceiver
Appendix A. Questions and Answers
(continued)
K2 Interface
Q31
: How are powerdown and warm start performed in
the T7264
A31
: The powerdown/warmstart sequence is as fol-
lows:
I
At the LT, the series of events begins with the
assertion of ldea = 1. This causes the device to
begin the automatic deactivation sequence. As
long as the device control bits (istp, lpbk, and
afrst) and the
RESET
and
ILOSS
pins remain
inactive during this time, the LT device con-
cludes deactivation by entering the powerdown
state. From this condition, the loop can be
reactivated by using a warm start.
I
At the NT, the device receives at least three
consecutive ldea = 0 bits from the LT during
deactivation. These bits must be read from the
K2 interface and interpreted to indicate that a
deactivation is occurring. Once this condition is
detected, the external controller must set
ldea = 1 at the NT, causing the device to freeze
its signal processor coefficients and power
down when a loss of signal from the LT is
detected. During this time, the device control
bits (istp, Ipbk, afrst, etc.) and the
RESET
and
ILOSS
pins must remain inactive at the NT.
From this condition, the loop can be reactivated
with a warm start.
Q32
: Does the device automatically reset and attempt
a cold start if out of frame (oof) occurs after a
warm start
A32
: When an oof condition occurs, the device enters
a reframing algorithm and attempts to regain syn-
chronization. During this time, the device is still
active. If, after 480 ms, the device has not
regained synchronization, it goes into the deac-
tive state, from which the next start-up attempt
will result in a cold start. This conforms to the
state tables shown in Appendix C of ANSI
T1.601.
Q33
: What is the purpose of the sksi bit in the device
control (DC) octet
A33
: Its primary use is to detect a “stuck at one” condi-
tion on the K2 interface. It is reflected back onto
the K2 interface as rsksi in the DS octet. Setting
sksi to 0 will guarantee that at least one bit (rsksi)
will be zero on the received K2 interface.
Q34
: What should the state of the other bits in the DC
octet be during a local U-loopback
A34
: To perform a loopback, the following sequence of
bits are set in the DC octet, where 1 resets the
device and puts it into a known state, 2 asserts
the loopback, and 3 resets the chip again and
removes the loopback. The other DC bits should
be kept in their inactive state:
Q35
: What is the state of the DO bits when OSYNC
goes low momentarily after the link is up
A35
: The 2B+D data and U-overhead bits are passed
transparently from the U-interface to the K2
interface. Since this U-information is likely to be
invalid during this time, the system should recog-
nize this and disregard the data and overhead
bits during this time. Note that this situation is dif-
ferent than when OSYNC is low prior to a start-
up. In the latter case, the 2B+D and overhead bits
are internally overwritten by the transceiver to
default values until synchronization is achieved
(see the data sheet for these values). In either
case, the DS bits are always valid.
Q36
: ANSI requires 0.75 ms to process the eoc mes-
sage at the NT before echoing it. The T7264 data
sheet, however, states that the time from when
an incoming message becomes available and the
next message goes out is 1.75 ms. How can the
T7264 meet the standard
A36
: The 0.75 ms in the ANSI requirement refers to
the delay between the start of the received
U frame and the start of the transmitted U frame.
In the eoc bit locations, there are SW/ISW plus
12 2B+D blocks of data between the last bit of
one eoc message and the first bit of the next one.
This provides an additional 1.46 ms of processing
time or a total of 2.21 ms. Of course, some of this
time is consumed by the T7264 in moving data
between the U and K2 interfaces. After these
delays are taken into consideration, 1.75 ms
remain to process data.
1. afrst = 1, Ipbk = x, istp = 1, xpcy = x [loopback
= inactive]
2. afrst = 0, Ipbk = 0, istp = 1, xpcy = x [loopback
= active]
3. afrst = 1, Ipbk = 1, istp = 1, xpcy = x [loopback
= inactive]
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