參數(shù)資料
型號(hào)： T7264
英文描述： T7264 U-Interface 2B1Q Transceiver
中文描述： T7264 U型接口2B1Q收發(fā)器
文件頁數(shù)： 17/54頁
文件大小： 876K
代理商： T7264
Data Sheet
April 1998
T7264 U-Interface 2B1Q Transceiver
Lucent Technologies Inc.
17
K2 Interface Description
(continued)
Table 9. UM2 and UM3 Octet—UCS Bits (Overview)
Table 10. UM2 and UM3 Octet—UCS Bits (Functions)
Octet
UM2
UM2
UM3
UM3
Octet #
6
6
7
7
DO/DI
DO
LT
/[DI
NT
]
DO
NT
/[DI
LT
]
DO
LT
/[DI
NT
]
DO
NT
/[DI
LT
]
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
act
act
cso
R
5, 4
Bit 6
R
1, 5
R
1, 5
R
6, 4
R
6, 4
Bit 7
R
1, 6
R
1, 6
sai
uoa
Bit 8
ps1
[a]dea
nib
aib
See previous page.
See previous page.
[r]febe
[r]febe
R
2, 5
R
2, 5
ps2
R
3, 4
ntm
R
4, 4
Octet
UM2
Bit #
5
Symbol
act
Name/Function
Activation.
Passed transparently from the K2 to the U-interface and from the U to the
K2 except during a start-up when it is forced to a 0 on the K2.
0—Pending activation.
1—Ready to transmit information.
Reserved Bits.
Passed transparently from the K2 to the U-interface and from the U
to the K2. Transmit should always be set to a 1.
Power Status #1.
Passed transparently from the K2 to the U-interface at the NT and
from the U to the K2 at the LT.
0—Primary power out.
1—Primary power is normal.
When both ps1 and ps2 are 0, this indicates a dying gasp.
[AND with] Deactivate.
In LT mode, this bit is used in conjunction with the ldea bit
from the K2, then passed to the U-interface as the transmitted dea bit. In NT mode,
this bit is passed transparently from the U to the K2 interface. Allows deactivation
warning to the far-end NT without deactivating the local transceiver.
0—Deactivation warning.
1—Normal.
Reserved Bits.
Passed transparently from the K2 to the U-interface and from the U
to the K2 interface. Transmit should always be set to a 1.
[Receive] Far-End Block Error.
If the MODE1 = 1, rfebe is ANDed with nebe and the
result is sent out as the U-interface febe bit. If the MODE1 = 0, rfebe is passed trans-
parently from the K2 (DO
LT
/DI
NT
) to the U-interface febe bit. For either setting of
MODE1, the febe bit is passed transparently from the U-interface to the K2 interface.
0—Error indication passed to the originator.
1—No error, or feature is not utilized.
Power Status #2.
Passed transparently from the K2 to the U-interface at the NT and
from the U to the K2 at the LT.
0—Secondary power out.
1—Secondary power normal.
When both ps1 and ps2 are 0, this indicates a dying gasp.
NT Test Mode.
Passed transparently from the K2 to the U-interface at the NT and
from the U to the K2 at the LT.
0—The NT is currently in a test mode.
1—Normal.
UM2
6, 7
R
x, y
UM2
8
ps1
(DO
LT
/
DI
NT
)
UM2
8
[a]dea
(DO
NT
/
DI
LT
)
UM3
1, 6
R
x, y
UM3
2
[r]febe
UM3
3
ps2
(DO
LT
/
DI
NT
)
UM3
4
ntm
(DO
LT
/
DI
NT
)
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