參數(shù)資料
型號： T7264
英文描述： T7264 U-Interface 2B1Q Transceiver
中文描述： T7264 U型接口2B1Q收發(fā)器
文件頁數(shù)： 2/54頁
文件大?。?/td> 876K
代理商： T7264
Table of Contents
Contents
Page
Contents
Page
2
Lucent Technologies Inc.
Data Sheet
April 1998
T7264 U-Interface 2B1Q Transceiver
Features ..........................................................................1
Description .......................................................................1
Pin Information ................................................................3
Functional Overview.........................................................6
Device Interface and Connections....................................7
Analog Device Interface ................................................7
Power Supply Connections............................................8
Clock Operation.............................................................8
Reset Operation.............................................................8
Reset Sequences and Clock Synchronization............8
Reset Time..................................................................9
Idle Mode.....................................................................10
NT Maintenance ..........................................................10
K2 Interface Description ................................................11
K2 NT and LT Timing Sources.....................................12
K2 Bits Description ......................................................13
K2 Bit Levels................................................................20
U-Interface Description ..................................................21
K2 Functional Description ..............................................22
K2 Framing Bits ...........................................................23
K2 eoc and Loopback Response Timing ....................24
K2 Device Status and Control Bits...............................25
The adea Bit ................................................................26
The nebe, febe, rfebe, and ccrc Bits............................27
NT or LT Operation ........................................................28
Minimal Example............................................................29
Activation and the K2 Interface ......................................30
Priority .........................................................................31
Applications....................................................................32
Absolute Maximum Ratings ...........................................34
Handling Precautions .....................................................34
Recommended Operating Conditions ............................34
Electrical Characteristics ...............................................35
Loop-Range Performance Characteristics .....................36
Timing Characteristics ...................................................37
Switching Test Input/Output Waveform ..........................38
Outline Diagram .............................................................39
Ordering Information ......................................................39
Appendix A. Questions and Answers ............................40
Introduction..................................................................40
U-Interface...................................................................40
K2 Interface ................................................................46
Miscellaneous .............................................................49
Appendix B. Differences Between the T-7264- - -ML,
T-7264- - -ML2 and T-7264A- -ML Devices ...................53
Technology...................................................................53
Standard......................................................................53
List of Figures
Figure 1. T7264 Simplified Block Diagram .......................1
Figure 2. Pin Diagram ......................................................3
Figure 3. Quat Example ...................................................6
Figure 4. Line Interface and Protection ............................7
Figure 5. Recommended Power Supply
Connections ..................................................................8
Figure 6. RESET Waveform Normal Operation ...............9
Figure 7. RESET Timing for Synchronized Clocks ..........9
Figure 8. K2 Interface Timing .........................................11
Figure 9. K2 Octets ........................................................11
Figure 10. K2 Interface LT and NT .................................12
Figure 11. K2 Interface Frame Format ...........................14
Figure 12. U-Interface Frame and Superframe ..............21
Figure 13. U-Interface Superframe Bit Groups ..............21
Figure 14. K2 Octet Description .....................................22
Figure 15. K2 Functional Description .............................22
Figure 16. K2-to-U Mapping ...........................................23
Figure 17. U-to-K2 Mapping ...........................................24
Figure 18. K2 Response Timing .....................................24
Figure 19. T7264 nebe/febe/crc Block Diagram .............28
Figure 20. Use of rfebe in a Multilink Configuration .......28
Figure 21. State Sequence for DSL Transceiver
Start-Up .......................................................................32
Figure 22. Loop Application ...........................................33
Figure 23. 2-Wire Terminal Application ..........................33
Figure 24. Digital Pair Gain Application .........................33
Figure 25. Timing Diagram Referenced to F ..................37
Figure 26. Timing Diagram Referenced to C ..................37
Figure 27. RESET Timing Diagram ................................38
Figure 28. Switching Test Waveform ..............................38
List of Tables
Table 1. Pin Functions ......................................................3
Table 2. Pin Descriptions ..................................................4
Table 3. Clock Configuration ............................................6
Table 4. K2 Interface Serial Data Bit Map ......................13
Table 5. B1, B2, D, and S1 Octets (Overview) ...............15
Table 6. B1, B2, D, and S1 Octets (Functions) ...............15
Table 7. UM1 and UM2 Octets—eoc Bits (Overview) ....16
Table 8. UM1 and UM2 Octets—eoc Bits (Functions) ....16
Table 9. UM2 and UM3 Octet—UCS Bits (Overview) ....17
Table 10. UM2 and UM3 Octet—UCS Bits (Functions) ..17
Table 11. DS Octet (Overview)—Device Status .............18
Table 12. DS Octet (Functions)—Device Status ............18
Table 13. DC Octet (Overview) ......................................19
Table 14. DC Octet (Functions) ......................................19
Table 15. K2 Data Out (DO) Bit Levels ...........................20
Table 16. K2 Device Control (DC) Bit Levels ..................20
Table 17. U-Interface Bit Assignment .............................22
Table 18. DC Octet Description (Control) .......................25
Table 19. DS Octet Description (Status) ........................25
Table 20. adea, ldea, and dea Function .........................26
Table 21. MODE0 Pin Functionality ...............................28
Table 22. Minimal Implementation ..................................29
Table 23. Definitions of Signals During Start-Up ............31
Table 24. Power Consumption .......................................35
Table 25. Performance Ratings ......................................35
Table 26. Crystal Characteristics: Fundamental
Mode Crystal ...............................................................35
Table 27. Internal PLL Characteristics ...........................36
Table 28. Digital dc Characteristics (Over Operating
Ranges) ......................................................................36
Table 29. Clock Timing ...................................................37
Table 30. MTC Requirements and Characteristics
(LT Mode) ....................................................................38
Table 31. RESET Timing................................................ 38
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