參數(shù)資料
型號(hào)： T7264
英文描述： T7264 U-Interface 2B1Q Transceiver
中文描述： T7264 U型接口2B1Q收發(fā)器
文件頁(yè)數(shù)： 49/54頁(yè)
文件大?。?/td> 876K
代理商： T7264
Lucent Technologies Inc.
49
Data Sheet
April 1998
T7264 U-Interface 2B1Q Transceiver
Appendix A. Questions and Answers
(continued)
Miscellaneous
Q45
: Does the T7264 have a second source
A45
: It is manufactured at multiple Lucent ME loca-
tions, but no second source outside Lucent is
currently available.
Q46
: Are digital I/Os TTL or CMOS compatible
A46
: Both. All I/Os are CMOS. They are specified at
TTL because the current requirement makes this
more difficult to meet. At higher output voltages,
the current will be less, perhaps 100 mA at 3.5 V.
Q47
: What is the current sinking capability of OSYNC
A47
: The OSYNC lead supports a standard TTL load
and will sink (or source) 1.6 mA.
Q48
: What are the tolerances of the various discrete
components around the chip set
A48
: Discrete components and their tolerances are as
follows:
Q49
: If a switching power regulator is used in the
system, is there a frequency to which it should be
set
A49
: A switching frequency of 80 kHz or higher
multiples, synchronous to the 2B1Q band clock,
would be optimal. An 80 kHz clock is available at
pin 43 that is synchronous with the 2B1Q signals.
Q50
: Please explain how to use the
FFC
pin in detail
and its purpose.
A50
: The
FFC
pin can be used in applications where
the MTC clock is switched from one source to
another and may have glitches during the switch.
One example of this is in DLC applications when
the system switches to a protection clock board,
and a new MTC clock is used. Before the protec-
tion switch,
FFC
should be brought low to freeze
the internal states of the timing recovery circuitry.
After the new clock has stabilized,
FFC
can be
brought high again and the T7264 circuitry will
lock to the new clock without dropping the U-
interface. Without the
FFC
function, the U-inter-
face might be dropped while the new clock is
being applied.
Q51
: What is the meaning of free-running and phase-
locked in Table 3 of this data sheet
A51
: In Table 3, CKOUT is defined to be either
3-stated, 15.36 MHz free-running, 7.68 MHz free-
running, or 10.24 MHz phase-locked. Free-run-
ning means that the CKOUT clock is directly
derived from the 15.36 MHz crystal oscillator
clock that is not synchronous with the U-interface
line rate. Phase-locked means that the
10.24 MHz CKOUT clock is synchronous with the
U-interface line rate. This clock does not have
50% duty cycle, and will experience occasional
duty-cycle adjustments (i.e., phase steps) to
keep it synchronous with the U-interface. (See
the note at the bottom of Table 3 in the data
sheet.)
Q52
: What are the filter characteristics of the PLL at
the NT
A52
: The –3 dB frequency is approximately 5 Hz;
peaking is about 1.2 dB.
Q53
: Is it possible to get a T7264-based LT to operate
properly with a NT without supplying an MTC
clock
A53
: Yes. Tying MTC to +5 V will yield a
±
100 ppm
MTC, which a Lucent NT will be able to lock to in
most cases. This configuration should be used for
laboratory purposes only. For all serious perfor-
mance testing, a
±
32 ppm (or better) MTC should
be used.
Q54
: If there are several NT-mode T7264s on a board,
can only one crystal be used to run them
A54
: Yes. The following is an explanation of how this is
accomplished (refer to Table 3 on page 6 of this
data sheet). First, connect a crystal in the normal
fashion to one T7264; the V
DDO
, MCLK, and
CKSEL pins should be set per the first entry in
Table 3 (+5/0/0). Now set the V
DDO
, MCLK, and
CKSEL pins on all the other T7264s as per the
last entry in Table 3 (0/15.36/1), and use the
15.36 MHz signal coming from CKOUT (pin 23)
of the first T7264 to provide the 15.36 MHz input
to MCLK (pin 24) on the others.
Line-Side Resistors
dc Blocking Capacitor
Device-Side Resistors
Bypass Capacitors
Bypass Capacitors
16.9
±
7%
1.0
μ
F
±
5%
16.9
±
1%
0.1
μ
F
±
10%
1.0
μ
F
±
10%
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