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參數(shù)資料
| 型號： | T7264 |
| 英文描述： | T7264 U-Interface 2B1Q Transceiver |
| 中文描述： | T7264 U型接口2B1Q收發(fā)器 |
| 文件頁數(shù)： | 50/54頁 |
| 文件大?。?/td> | 876K |
| 代理商： | T7264 |
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50
Lucent Technologies Inc.
Data Sheet
April 1998
T7264 U-Interface 2B1Q Transceiver
Appendix A. Questions and Answers
(continued)
Q55
: Will the T7264 run in NT mode with the K2 clock
slaved to an external backplane
A55
: The T7264 does not support this mode. For those
applications where this is an issue, systems
designers have generally provided some elastic
store on the K2-to-backplane ASIC. The elastic
store must be sized according to the amount of
jitter which can be introduced into a system and
the amount of jitter gain in the system APLLs.
For example, assume that the backplane clock is
derived from a recovered T1 clock. The worst-
case jitter for a T1 line is 0.259 UI at frequencies
of 0.001 Hz—10 Hz. Considering that an LT-
mode T7264 APLL has jitter peaking of 0.4 dB at
0.15 Hz, the 0.259 UI of jitter could be amplified
to 0.271 UI. Since 0.271 UI of 80 kHz is 3.39
μ
s,
this is how much elastic store is required.
Note that this is a simplified example: there may
be other APLLs in the system (for example, the
T1-to-backplane clock APLL), and their peaking
must be factored in also. In addition, it is
desirable to design in some margin.
Q56
: Is there a recommended method for powering the
T7264 For example, is it desirable to separate
the power supplies, etc.
A56
: The T7264 is not extremely sensitive to power
supply schemes. Following standard practices of
decoupling power supplies close to the chip and,
if power and ground planes are not used, keeping
power traces away from high-frequency signals,
etc., should yield acceptable results. Separating
the T7264 analog power supplies from the digital
power supplies near the chip can yield a small
improvement, and the same holds true for using
power and ground planes vs. discrete traces.
Note
: If analog and digital power supplies are
separated, the XTAL power supply (V
DDO
)
should be tied to the digital supplies
(V
DDD
).
Q57
: What is the effect of ramping down the power
supply voltage on the device When will it provide
a valid reset This condition can occur when a
line-powered NT1’s line cord is repeatedly
plugged in and removed and plugged in again
before the power supply has had enough time to
fully ramp up.
A57
: The device’s reset is more dependent on the
RESET
pin than the power supply to the device.
As long as the proper input conditions on the
RESET
pin (see Table 32) are met, the device will
have a valid reset. Note that this input is a
Schmitt-trigger input.
Q58
: Does the output jitter of the 9 kHz F clock on an
NT-mode T7264 meet the 5% peak-to-peak jitter
requirement described in ITU-T I.430, Section
8.3, assuming the S/T transceiver is the T7252A
A58
: Yes, the 5% requirement applies to high-
frequency jitter (>50 Hz) at the NT. The T7264
produces approximately 100 ns of high-frequency
jitter in the NT mode on F, and the T7252A can
accept up to 160 ns of high-frequency jitter on its
input clock and still meet the I.430 requirement.
Q59
: What should be known before having a T7264-
based product conformance tested at Bellcore
A59
: A copy of the Bellcore Test Bed Interface Specifi-
cation should be obtained from Bellcore to get
the latest requirements.
The Bellcore specification, when last reviewed by
Lucent, required that a unit under test provide
access to the following signals or state indicators.
(The T7264 pin name in upper case, or K2 bit
name, lower case, which corresponds to the
Bellcore-required signal, is enclosed in braces.)
Transceiver Status Signals
:
Fully operational state indicator {oof or OSYNC}
Full reset state indicator
Loss-of-frame alignment (opt)
RX crc check indicator (opt)
{xact}
{oof or OSYNC}
{nebe}
Transceiver Control Signals
:
Transceiver full reset
Transceiver activation
LT transceiver deactivation
Transmit M1—M4 bit control
Transmit 2B+D payload gating {received act}
Continuous scrambled output
test mode
{
RESET
}
{istp}
{ldea}
{K2 access}
{
ILOSS
at NT}
{Ipbk at LT}
Intertransceiver Signals (LT only)
:
Superframe timing
2.56 MHz clock
{conditioned tsf}
{CKOUT/4}
Note
: T7264 must be optioned for a 10.24 MHz
CKOUT.
2B+D Test Access
18-bit bursted clock and corresponding 2B+D
serial data stream must be accessible in both
transmit and receive directions.
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