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參數(shù)資料
| 型號： | T7264 |
| 英文描述： | T7264 U-Interface 2B1Q Transceiver |
| 中文描述： | T7264 U型接口2B1Q收發(fā)器 |
| 文件頁數(shù)： | 48/54頁 |
| 文件大?。?/td> | 876K |
| 代理商： | T7264 |
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48
Lucent Technologies Inc.
Data Sheet
April 1998
T7264 U-Interface 2B1Q Transceiver
Appendix A. Questions and Answers
(continued)
Q39
: What is the relationship between istp and ldea
A39
: The istp bit should be set to 1 before or at the
same time as ldea is set to 1. Once the chip set is
deactivated, setting istp to 0 for at least three K2
frames will initiate start-up. However, it is neces-
sary for ldea to be 0 before time T7 (see ANSI
Table 5, Figure 16) for the start-up process to be
successfully completed.
Q40
: When should nebes and febes be counted
A40
: During activation, nebes and febes will occur at
each end of the link between the time framing is
initially achieved and the time the link is fully
operational at each end. These nebe/febe
occurrences are normal and are of no interest.
Therefore, nebe/febe counters should be reset to
zero after the link is fully operational. This is most
easily achieved by delaying about 500 ms after
getting oof = 1 and then resetting the nebe/febe
counters.
Q41
: How is the D+ channel for 3-DS0 TDM applica-
tions generated (Bellcore TR-TSY-000397)
A41
: Since the crc bits are not passed to the K2 inter-
face, the D+ channel cannot be formed directly;
those bits must be generated externally. Also, a
recent standard ballot addressed this issue by
noting that, in general, the form of the D+ channel
is application-dependent, so a broad standard is
not being developed.
Q42
: How does RSF behave during a reframe
A42
: RSF behavior is transparent to the oof (out-of-
frame) condition. Whenever the chip thinks it has
found an ISW, it forces RSF high. RSF stays high
for 12 K2 frames, at which point it goes low until
the occurrence of the next ISW.
Q43
: Does the K2 F clock do anything strange when a
RESET
is asserted This clock is being used to
initialize an elastic store, and it seems to be pro-
ducing some strange glitches.
A43
: There are two ways to reset the chip:
1. Assert the
RESET
pin low.
2. Assert the K2 afrst bit (DC octet) high.
The difference between these two resets is that
#1 resets the entire chip, including the on-chip
PLL, while #2 resets everything except the PLL.
Therefore, for both resets, the counter which con-
trols the frequency gets loaded to its initial value,
but the counter which controls the phase only
gets reset when the
RESET
pin is asserted.
In the case described, this means that with either
reset #1 or #2, the frequency counter controlling
F will be reinitialized, which could cause a
strange duty cycle on F for one clock period. But
once this initialization occurs, the F clock immedi-
ately starts behaving normally, even if the
RESET
control remains active (also, in the case of reset
#1, the PLL starts to acquire). From a system
standpoint, you can always count on F behaving
predictably when
RESET
is released because
reset #1 or #2 must be asserted for at least 3 K2
frames, and the F clock duty cycle will stabilize
after one K2 frame. So any logic for an elastic
store which uses F should initialize upon exit from
the reset state. However, be sure to consider the
effect the shift in F may have on other parts of the
system.
Q44
: What is the phase relationship between MTC and
F at the LT
A44
: F is phase-locked to MTC by a second-order PLL
that has a –3 dB frequency of approximately
0.5 Hz and has about 0.4 dB of peaking.
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