參數(shù)資料
型號: ST72321BM
廠商: 意法半導體
英文描述: 80-PIN 8-BIT MCU WITH 32 TO 60K FLASH/ROM, ADC, FIVE TIMERS, SPI, SCI, I2C INTERFACE(具有ICP,IAP,Nested Interrupt,TLI,ROP的8位MCU)
中文描述: 80引腳8位微控制器32至60,000閃存/ ROM,ADC的,5個定時器,SPI和SCI的I2C接口(具有比較方案,國際檢察官聯(lián)合會,嵌套中斷,中華語文研習所,人事登記的8位微控制器)
文件頁數(shù): 84/178頁
文件大?。?/td> 3121K
代理商: ST72321BM
ST72F321M, ST72321BM
84/178
9.5 SERIAL PERIPHERAL INTERFACE (SPI)
9.5.1 Introduction
The Serial Peripheral Interface (SPI) allows full-
duplex, synchronous, serial communication with
external devices. An SPI system may consist of a
master and one or more slaves however the SPI
interface can not be a master in a multi-master
system.
9.5.2 Main Features
Full duplex synchronous transfers (on 3 lines)
Simplex synchronous transfers (on 2 lines)
Master or slave operation
Six master mode frequencies (f
CPU
/4 max.)
f
CPU
/2 max. slave mode frequency (see note)
SS Management by software or hardware
Programmable clock polarity and phase
End of transfer interrupt flag
Write collision, Master Mode Fault and Overrun
flags
Note:
In slave mode, continuous transmission is
not possible at maximum frequency due to the
software overhead for clearing status flags and to
initiate the next transmission sequence.
9.5.3 General Description
Figure 50
shows the serial peripheral interface
(SPI) block diagram. There are 3 registers:
– SPI Control Register (SPICR)
– SPI Control/Status Register (SPICSR)
– SPI Data Register (SPIDR)
The SPI is connected to external devices through
4 pins:
– MISO: Master In / Slave Out data
– MOSI: Master Out / Slave In data
– SCK: Serial Clock out by SPI masters and in-
put by SPI slaves
Figure 50. Serial Peripheral Interface Block Diagram
SPIDR
Read Buffer
8-Bit Shift Register
Write
Read
Data/Address Bus
SPI
STATE
SPIE
SPE
MSTR
CPHA
SPR0
SPR1
CPOL
SERIAL CLOCK
GENERATOR
MOSI
MISO
SS
SCK
CONTROL
SPICR
SPICSR
Interrupt
request
MASTER
CONTROL
SPR2
0
7
0
7
SPIF WCOL
MODF
0
OVR
SSI
SSM
SOD
SOD
bit
SS
1
0
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