參數資料
型號: ST72321BM
廠商: 意法半導體
英文描述: 80-PIN 8-BIT MCU WITH 32 TO 60K FLASH/ROM, ADC, FIVE TIMERS, SPI, SCI, I2C INTERFACE(具有ICP,IAP,Nested Interrupt,TLI,ROP的8位MCU)
中文描述: 80引腳8位微控制器32至60,000閃存/ ROM,ADC的,5個定時器,SPI和SCI的I2C接口(具有比較方案,國際檢察官聯合會,嵌套中斷,中華語文研習所,人事登記的8位微控制器)
文件頁數: 62/178頁
文件大?。?/td> 3121K
代理商: ST72321BM
ST72F321M, ST72321BM
62/178
ON-CHIP PERIPHERALS
(Cont’d)
PWM CONTROL REGISTER (PWMCR)
Read/Write
Reset Value: 0000 0000 (00h)
Bit 7:4 =
OE[3:0]
PWM Output Enable
These bits are set and cleared by software. They
enable or disable the PWM output channels inde-
pendently acting on the corresponding I/O pin.
0: PWM output disabled.
1: PWM output enabled.
Bit 3:0 =
OP[3:0]
PWM Output Polarity
These bits are set and cleared by software. They
independently select the polarity of the four PWM
output signals.
Note
: When an OPx bit is modified, the PWMx out-
put signal polarity is immediately reversed.
DUTY CYCLE REGISTERS (PWMDCRx)
Read/Write
Reset Value: 0000 0000 (00h)
Bit 7:0 =
DC[7:0]
Duty Cycle Data
These bits are set and cleared by software.
A PWMDCRx register is associated with the OCRx
register of each PWM channel to determine the
second edge location of the PWM signal (the first
edge location is common to all channels and given
by the ARTARR register). These PWMDCR regis-
ters allow the duty cycle to be set independently
for each PWM channel.
7
0
OE3
OE2
OE1
OE0
OP3
OP2
OP1
OP0
PWMx output level
OPx
Counter <= OCRx
Counter > OCRx
1
0
0
1
0
1
7
0
DC7
DC6
DC5
DC4
DC3
DC2
DC1
DC0
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