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| 型號： | ST72321BM |
| 廠商： | 意法半導體 |
| 英文描述： | 80-PIN 8-BIT MCU WITH 32 TO 60K FLASH/ROM, ADC, FIVE TIMERS, SPI, SCI, I2C INTERFACE(具有ICP,IAP,Nested Interrupt,TLI,ROP的8位MCU) |
| 中文描述： | 80引腳8位微控制器32至60,000閃存/ ROM，ADC的，5個定時器，SPI和SCI的I2C接口（具有比較方案，國際檢察官聯(lián)合會，嵌套中斷，中華語文研習所，人事登記的8位微控制器） |
| 文件頁數(shù)： | 173/178頁 |
| 文件大?。?/td> | 3121K |
| 代理商： | ST72321BM |
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ST72F321M, ST72321BM
173/178
14 KNOWN LIMITATIONS
14.1 ALL FLASH AND ROM DEVICES
14.1.1 Safe Connection of OSC1/OSC2 Pins
The OSC1 and/or OSC2 pins must not be left un-
connected otherwise the ST7 main oscillator may
start and, in this configuration, could generate an
f
OSC
clock frequency in excess of the allowed
maximum (>16MHz.), putting the ST7 in an un-
safe/undefined state. Refer to
section 6.2 on page
24
.
14.1.2 Reset pin protection with LVD Enabled
As mentioned in note 2 below
Figure 86 on page
156
, when the LVD is enabled, it is recommended
not to connect a pull-up resistor or capacitor. A
10nF pull-down capacitor is required to filter noise
on the reset line.
14.1.3 Unexpected Reset Fetch
If an interrupt request occurs while a “POP CC” in-
struction is executed, the interrupt controller does
not recognise the source of the interrupt and, by
default, passes the RESET vector address to the
CPU.
Workaround
To solve this issue, a “POP CC” instruction must
always be preceded by a “SIM” instruction.
14.1.4 External interrupt missed
To avoid any risk if generating a parasitic interrupt,
the edge detector is automatically disabled for one
clock cycle during an access to either DDR and
OR. Any input signal edge during this period will
not be detected and will not generate an interrupt.
This case can typically occur if the application re-
freshes the port configuration registers at intervals
during runtime.
Workaround
The workaround is based on software checking
the level on the interrupt pin before and after writ-
ing to the PxOR or PxDDR registers. If there is a
level change (depending on the sensitivity pro-
grammed for this pin) the interrupt routine is in-
voked using the call instruction with three extra
PUSH instructions before executing the interrupt
routine (this is to make the call compatible with the
IRET instruction at the end of the interrupt service
routine).
But detection of the level change does not make
sure that edge occurs during the critical 1 cycle du-
ration and the interrupt has been missed. This may
lead to occurrence of same interrupt twice (one
hardware and another with software call).
To avoid this, a semaphore is set to '1' before
checking the level change. The semaphore is
changed to level '0' inside the interrupt routine.
When a level change is detected, the semaphore
status is checked and if it is '1' this means that the
last interrupt has been missed. In this case, the in-
terrupt routine is invoked with the call instruction.
There is another possible case i.e. if writing to
PxOR or PxDDR is done with global interrupts dis-
abled (interrupt mask bit set). In this case, the
semaphore is changed to '1' when the level
change is detected. Detecting a missed interrupt is
done after the global interrupts are enabled (inter-
rupt mask bit reset) and by checking the status of
the semaphore. If it is '1' this means that the last
interrupt was missed and the interrupt routine is in-
voked with the call instruction.
To implement the workaround, the following soft-
ware sequence is to be followed for writing into the
PxOR/PxDDR registers. The example is for for
Port PF1 with falling edge interrupt sensitivity. The
software sequence is given for both cases (global
interrupt disabled/enabled).
Case 1:
Writing to PxOR or PxDDR with Global In-
terrupts Enabled:
LD A,#01
LD sema,A
; set the semaphore to '1'
LD A,PFDR
AND A,#02
LD X,A
; store the level before writing to
PxOR/PxDDR
LD A,#$90
LD PFDDR,A ; Write to PFDDR
LD A,#$ff
LD PFOR,A
; Write to PFOR
LD A,PFDR
AND A,#02
LD Y,A
; store the level after writing to
PxOR/PxDDR
LD A,X
; check for falling edge
cp A,#02
jrne OUT
TNZ Y
jrne OUT
LD A,sema
; check the semaphore status if
edge is detected
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| ST72321BR6-AUTO | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-bit MCU for automotive with 32 to 60 Kbyte Flash/ROM, ADC, 5 timers, SPI, SCI, I2C interface |
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| ST72321J | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, 5 TIMERS, SPI, SCI, I2C INTERFACE |
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