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參數(shù)資料
| 型號： | ST72321BM |
| 廠商： | 意法半導體 |
| 英文描述： | 80-PIN 8-BIT MCU WITH 32 TO 60K FLASH/ROM, ADC, FIVE TIMERS, SPI, SCI, I2C INTERFACE(具有ICP,IAP,Nested Interrupt,TLI,ROP的8位MCU) |
| 中文描述： | 80引腳8位微控制器32至60,000閃存/ ROM，ADC的，5個定時器，SPI和SCI的I2C接口（具有比較方案，國際檢察官聯(lián)合會，嵌套中斷，中華語文研習所，人事登記的8位微控制器） |
| 文件頁數(shù)： | 31/178頁 |
| 文件大?。?/td> | 3121K |
| 代理商： | ST72321BM |
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ST72F321M, ST72321BM
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SYSTEM INTEGRITY MANAGEMENT
(Cont’d)
6.4.4 Register Description
SYSTEM INTEGRITY (SI) CONTROL/STATUS REGISTER (SICSR)
Read/Write
Reset Value: 000x 000x (00h)
Bit 7 =
AVDS
Voltage Detection selection
This bit is set and cleared by software. Voltage De-
tection is available only if the LVD is enabled by
option byte.
0: Voltage detection on V
DD
supply
1: Voltage detection on EVD pin
Bit 6 =
AVDIE
Voltage Detector interrupt enable
This bit is set and cleared by software. It enables
an interrupt to be generated when the AVDF flag
changes (toggles). The pending interrupt informa-
tion is automatically cleared when software enters
the AVD interrupt routine.
0: AVD interrupt disabled
1: AVD interrupt enabled
Bit 5 =
AVDF
Voltage Detector flag
This read-only bit is set and cleared by hardware.
If the AVDIE bit is set, an interrupt request is gen-
erated when the AVDF bit changes value. Refer to
Figure 15
and to
Section 6.4.2.1
for additional de-
tails.
0: V
DD
or V
EVD
over V
IT+(AVD)
threshold
1: V
DD
or V
EVD
under V
IT-(AVD)
threshold
Bit 4 =
LVDRF
LVD reset flag
This bit indicates that the last Reset was generat-
ed by the LVD block. It is set by hardware (LVD re-
set) and cleared by software (writing zero). See
WDGRF flag description for more details. When
the LVD is disabled by OPTION BYTE, the LVDRF
bit value is undefined.
Bits 3:1 = Reserved, must be kept cleared.
Bit 0 =
WDGRF
Watchdog reset flag
This bit indicates that the last Reset was generat-
ed by the Watchdog peripheral. It is set by hard-
ware (watchdog reset) and cleared by software
(writing zero) or an LVD Reset (to ensure a stable
cleared state of the WDGRF flag when CPU
starts).
Combined with the LVDRF flag information, the
flag description is given by the following table.
Application notes
The LVDRF flag is not cleared when another RE-
SET type occurs (external or watchdog), the
LVDRF flag remains set to keep trace of the origi-
nal failure.
In this case, a watchdog reset can be detected by
software while an external reset can not.
CAUTION:
When the LVD is not activated with the
associated option byte, the WDGRF flag can not
be used in the application.
7
0
AVD
S
AVD
IE
AVD
F
LVD
RF
0
0
0
WDG
RF
RESET Sources
LVDRF
WDGRF
External RESET pin
Watchdog
LVD
0
0
1
0
1
X
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