- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄382552 > ST72321BM (意法半導(dǎo)體) 80-PIN 8-BIT MCU WITH 32 TO 60K FLASH/ROM, ADC, FIVE TIMERS, SPI, SCI, I2C INTERFACE(具有ICP,IAP,Nested Interrupt,TLI,ROP的8位MCU) PDF資料下載
參數(shù)資料
| 型號： | ST72321BM |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 80-PIN 8-BIT MCU WITH 32 TO 60K FLASH/ROM, ADC, FIVE TIMERS, SPI, SCI, I2C INTERFACE(具有ICP,IAP,Nested Interrupt,TLI,ROP的8位MCU) |
| 中文描述： | 80引腳8位微控制器32至60,000閃存/ ROM，ADC的，5個定時器，SPI和SCI的I2C接口（具有比較方案，國際檢察官聯(lián)合會，嵌套中斷，中華語文研習(xí)所，人事登記的8位微控制器） |
| 文件頁數(shù)： | 43/178頁 |
| 文件大?。?/td> | 3121K |
| 代理商： | ST72321BM |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁當(dāng)前第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁
ST72F321M, ST72321BM
43/178
POWER SAVING MODES
(Cont’d)
8.4 ACTIVE-HALT AND HALT MODES
ACTIVE-HALT and HALT modes are the two low-
est power consumption modes of the MCU. They
are both entered by executing the ‘HALT’ instruc-
tion. The decision to enter either in ACTIVE-HALT
or HALT mode is given by the MCC/RTC interrupt
enable flag (OIE bit in MCCSR register).
8.4.1 ACTIVE-HALT MODE
ACTIVE-HALT mode is the lowest power con-
sumption mode of the MCU with a real time clock
available. It is entered by executing the ‘HALT’ in-
struction when the OIE bit of the Main Clock Con-
troller Status register (MCCSR) is set (see
section
9.2 on page 53
for more details on the MCCSR
register).
The MCU can exit ACTIVE-HALT mode on recep-
tion of an MCC/RTC interrupt or a RESET. In ROM
devices, external interrupts can be used to wake-
up the MCU. When exiting ACTIVE-HALT mode
by means of an interrupt, no 256 or 4096 CPU cy-
cle delay occurs. The CPU resumes operation by
servicing the interrupt or by fetching the reset vec-
tor which woke it up (see
Figure 26
).
When entering ACTIVE-HALT mode, the I[1:0] bits
in the CC register are forced to ‘10b’ to enable in-
terrupts. Therefore, if an interrupt is pending, the
MCU wakes up immediately.
In ACTIVE-HALT mode, only the main oscillator
and its associated counter (MCC/RTC) are run-
ning to keep a wake-up time base. All other periph-
erals are not clocked except those which get their
clock supply from another clock generator (such
as external or auxiliary oscillator).
The safeguard against staying locked in ACTIVE-
HALT mode is provided by the oscillator interrupt.
Note:
As soon as the interrupt capability of one of
the oscillators is selected (MCCSR.OIE bit set),
entering ACTIVE-HALT mode while the Watchdog
is active does not generate a RESET.
This means that the device cannot spend more
than a defined delay in this power saving mode.
CAUTION:
When exiting ACTIVE-HALT mode fol-
lowing an MCC/RTC interrupt, OIE bit of MCCSR
register must not be cleared before t
DELAY
after
the interrupt occurs (t
DELAY
= 256 or 4096 t
CPU
de-
lay depending on option byte). Otherwise, the ST7
enters HALT mode for the remaining t
DELAY
peri-
od.
Figure 25. ACTIVE-HALT Timing Overview
Figure 26. ACTIVE-HALT Mode Flow-chart
Notes:
1. This delay occurs only if the MCU exits ACTIVE-
HALT mode by means of a RESET.
2. Peripheral clocked with an external clock source
can still be active.
3. Before servicing an interrupt, the CC register is
pushed on the stack. The I[1:0] bits of the CC reg-
ister are set to the current software priority level of
the interrupt routine and restored when the CC
register is popped.
4. In flash devices only the MCC/RTC interrupt can
exit the MCU from ACTIVE-HALT mode.
MCCSR
OIE bit
Power Saving Mode entered when HALT
instruction is executed
0
1
HALT mode
ACTIVE-HALT mode
HALT
RUN
RUN
256 OR 4096 CPU
CYCLE DELAY
1)
RESET
OR
INTERRUPT
HALT
INSTRUCTION
[MCCSR.OIE=1]
FETCH
VECTOR
ACTIVE
HALT
INSTRUCTION
(MCCSR.OIE=1)
RESET
Y
N
N
Y
CPU
I[1:0] BITS
OSCILLATOR
PERIPHERALS
2)
ON
OFF
OFF
10
FETCH RESET VECTOR
OR SERVICE INTERRUPT
CPU
I[1:0] BITS
OSCILLATOR
PERIPHERALS
ON
OFF
ON
XX
3)
CPU
I[1:0] BITS
OSCILLATOR
PERIPHERALS
ON
ON
ON
XX
3)
256 OR 4096 CPU CLOCK
CYCLE DELAY
INTERRUPT
4)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ST72F321 | 64/44-PIN 8-BIT MCU WITH 32 TO 60K FLASH/ROM, ADC, FIVE TIMERS, SPI, SCI, I2C INTERFACE |
| ST72F321J7T6 | 64/44-PIN 8-BIT MCU WITH 32 TO 60K FLASH/ROM, ADC, FIVE TIMERS, SPI, SCI, I2C INTERFACE |
| ST72F321J7TA | 64/44-PIN 8-BIT MCU WITH 32 TO 60K FLASH/ROM, ADC, FIVE TIMERS, SPI, SCI, I2C INTERFACE |
| ST72F321AR6T6 | 64/44-PIN 8-BIT MCU WITH 32 TO 60K FLASH/ROM, ADC, FIVE TIMERS, SPI, SCI, I2C INTERFACE |
| ST72F321AR6TA | 64/44-PIN 8-BIT MCU WITH 32 TO 60K FLASH/ROM, ADC, FIVE TIMERS, SPI, SCI, I2C INTERFACE |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST72321BR6-AUTO | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-bit MCU for automotive with 32 to 60 Kbyte Flash/ROM, ADC, 5 timers, SPI, SCI, I2C interface |
| ST72321BR7-AUTO | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-bit MCU for automotive with 32 to 60 Kbyte Flash/ROM, ADC, 5 timers, SPI, SCI, I2C interface |
| ST72321BR9-AUTO | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-bit MCU for automotive with 32 to 60 Kbyte Flash/ROM, ADC, 5 timers, SPI, SCI, I2C interface |
| ST72321BXXX-AUTO | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-bit MCU for automotive with 32 to 60 Kbyte Flash/ROM, ADC, 5 timers, SPI, SCI, I2C interface |
| ST72321J | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, 5 TIMERS, SPI, SCI, I2C INTERFACE |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。