參數(shù)資料
型號： ST72321BM
廠商： 意法半導(dǎo)體
英文描述： 80-PIN 8-BIT MCU WITH 32 TO 60K FLASH/ROM, ADC, FIVE TIMERS, SPI, SCI, I2C INTERFACE(具有ICP,IAP,Nested Interrupt,TLI,ROP的8位MCU)
中文描述： 80引腳8位微控制器32至60,000閃存/ ROM，ADC的，5個定時器，SPI和SCI的I2C接口（具有比較方案，國際檢察官聯(lián)合會，嵌套中斷，中華語文研習(xí)所，人事登記的8位微控制器）
文件頁數(shù)： 53/178頁
文件大?。?/td> 3121K
代理商： ST72321BM
ST72F321M, ST72321BM
53/178
9.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK AND BEEPER (MCC/RTC)
The Main Clock Controller consists of three differ-
ent functions:
■
a programmable CPU clock prescaler
■
a clock-out signal to supply external devices
■
a real time clock timer with interrupt capability
Each function can be used independently and si-
multaneously.
9.2.1 Programmable CPU Clock Prescaler
The programmable CPU clock prescaler supplies
the clock for the ST7 CPU and its internal periph-
erals. It manages SLOW power saving mode (See
Section 8.2 SLOW MODE
for more details).
The prescaler selects the f
CPU
main clock frequen-
cy and is controlled by three bits in the MCCSR
register: CP[1:0] and SMS.
9.2.2 Clock-out Capability
The clock-out capability is an alternate function of
an I/O port pin that outputs a f
CPU
clock to drive
Figure 32. Main Clock Controller (MCC/RTC) Block Diagram
external devices. It is controlled by the MCO bit in
the MCCSR register.
CAUTION
: When selected, the clock out pin sus-
pends the clock during ACTIVE-HALT mode.
9.2.3 Real Time Clock Timer (RTC)
The counter of the real time clock timer allows an
interrupt to be generated based on an accurate
real time clock. Four different time bases depend-
ing directly on f
OSC2
are available. The whole
functionality is controlled by four bits of the MCC-
SR register: TB[1:0], OIE and OIF.
When the RTC interrupt is enabled (OIE bit set),
the ST7 enters ACTIVE-HALT mode when the
HALT instruction is executed. See
Section 8.4 AC-
TIVE-HALT AND HALT MODES
for more details.
9.2.4 Beeper
The beep function is controlled by the MCCBCR
register. It can output three selectable frequencies
on the BEEP pin (I/O port alternate function).
DIV 2, 4, 8, 16
MCC/RTC INTERRUPT
SMS
CP1 CP0
TB1
TB0
OIE
OIF
CPU CLOCK
TO CPU AND
PERIPHERALS
MCCSR
12-BIT MCC RTC
COUNTER
f
OSC2
f
CPU
MCO
MCO
BC1 BC0
MCCBCR
BEEP
SELECTION
BEEP SIGNAL
1
0
TO
WATCHDOG
TIMER
DIV 64
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