參數(shù)資料
型號： ST16C2552
廠商： Exar Corporation
英文描述： Dual UART with 16-Byte Transmit and Receive FIFO(雙通用異步接收器/發(fā)送器（帶16字節(jié)接收和發(fā)送先進先出）)
中文描述： 雙UART），16字節(jié)的傳輸和接收FIFO（雙通用異步接收器/發(fā)送器（帶16字節(jié)接收和發(fā)送先進先出）
文件頁數(shù)： 9/32頁
文件大小： 409K
代理商： ST16C2552
ST16C2552
9
Rev. 3.50
FIFO Operation
The 16 byte transmit and receive data FIFOs are
enabled by the FIFO Control Register (FCR) bit-0. The
user can set the receive trigger level via FCR bits 6/
7 but not the transmit trigger level. The transmit
interrupt trigger level is set to 16 following a reset. The
receiver FIFO section includes a time-out function to
ensure data is delivered to the external CPU. An
interrupt is generated whenever the Receive Holding
Register (RHR) has not been read following the load-
ing of a character or the receive trigger level has not
been reached.
Time-out Interrupts
The interrupts are enabled by IER bits 0-3. Care must
be taken when handling these interrupts. Following a
reset the transmitter interrupt is enabled, the 2552 will
issue an interrupt to indicate that transmit holding
register is empty. This interrupt must be serviced prior
to continuing operations. The LSR register provides
the current singular highest priority interrupt only. It
could be noted that CTS and RTS interrupts have
lowest interrupt priority. A condition can exist where a
higher priority interrupt may mask the lower priority
CTS/RTS interrupt(s). Only after servicing the higher
pending interrupt will the lower priority CTS/ RTS
interrupt(s) be reflected in the status register. Servic-
ing the interrupt without investigating further interrupt
conditions can result in data errors.
When two interrupt conditions have the same priority,
it is important to service these interrupts correctly.
Receive Data Ready and Receive Time Out have the
same interrupt priority (when enabled by IER bit-3).
The receiver issues an interrupt after the number of
characters have reached the programmed trigger
level. In this case the 2552 FIFO may hold more
characters than the programmed trigger level. Follow-
ing the removal of a data byte, the user should recheck
LSR bit-0 for additional characters. A Receive Time
Out will not occur if the receive FIFO is empty. The
time out counter is reset at the center of each stop bit
received or each time the receive holding register
(RHR) is read. The actual time out value is T (
T
ime out
length in bits) = 4 X P (
P
rogrammed word length) + 12.
To convert the time out value to a character value, the
user has to consider the complete word length, includ-
ing data information length, start bit, parity bit, and the
size of stop bit, i.e., 1X, 1.5X, or 2X bit times.
Example -A: If the user programs a word length of 7,
with no parity and one stop bit, the time out will be:
T = 4 X 7( programmed word length) +12 = 40 bit times.
The character time will be equal to 40 / 9 = 4.4
characters, or as shown in the fully worked out ex-
ample: T = [(programmed word length = 7) + (stop bit
= 1) + (start bit = 1) = 9]. 40 (bit times divided by 9) =
4.4 characters.
Example -B: If the user programs the word length = 7,
with parity and one stop bit, the time out will be:
T = 4 X 7(programmed word length) + 12 = 40 bit times.
Character time = 40 / 10 [ (programmed word length
= 7) + (parity = 1) + (stop bit = 1) + (start bit = 1) = 4
characters.
Programmable Baud Rate Generator
The 2552 supports high speed modem technologies
that have increased input data rates by employing
data compression schemes. For example a 33.6Kbps
modem that employs data compression may require a
115.2Kbps input data rate. A 128.0Kbps ISDN modem
that supports data compression may need an input
data rate of 460.8Kbps. The 2552 can support a
standard data rate of 921.6Kbps.
A single baud rate generator is provided for the
transmitter and receiver, allowing independent TX/RX
channel control. The programmable Baud Rate Gen-
erator is capable of accepting an input clock up to 24
MHz, as required for supporting a 1.5 Mbps data rate.
The 2552 can be configured for internal or external
clock operation. For internal clock oscillator opera-
tion, an industry standard microprocessor crystal (par-
allel resonant/ 20-33 pF load) is connected externally
between the XTAL1 and XTAL2 pins, with an external
1 M
resistor across it. Alternatively, an external
clock can be connected to the XTAL1 pin to clock the
internal baud rate generator for standard or custom
rates. (see Baud Rate Generator Programming).
The generator divides the input 16X clock by any
divisor from 1 to 2
16
-1. The 2552 divides the basic
external clock by 16. The basic 16X clock provides
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參數(shù)描述
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