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參數(shù)資料
| 型號(hào)： | ST16C2552 |
| 廠商： | Exar Corporation |
| 英文描述： | Dual UART with 16-Byte Transmit and Receive FIFO(雙通用異步接收器/發(fā)送器（帶16字節(jié)接收和發(fā)送先進(jìn)先出）) |
| 中文描述： | 雙UART），16字節(jié)的傳輸和接收FIFO（雙通用異步接收器/發(fā)送器（帶16字節(jié)接收和發(fā)送先進(jìn)先出） |
| 文件頁數(shù)： | 7/32頁 |
| 文件大?。?/td> | 409K |
| 代理商： | ST16C2552 |
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ST16C2552
7
Rev. 3.50
GENERAL DESCRIPTION
The 2552 provides serial asynchronous receive data
synchronization, parallel-to-serial and serial-to-paral-
lel data conversions for both the transmitter and
receiver sections. These functions are necessary for
converting the serial data stream into parallel data that
is required with digital data systems. Synchronization
for the serial data stream is accomplished by adding
start and stops bits to the transmit data to form a data
character (character orientated protocol). Data integ-
rity is insured by attaching a parity bit to the data
character. The parity bit is checked by the receiver for
any transmission bit errors. The electronic circuitry to
provide all these functions is fairly complex especially
when manufactured on a single integrated silicon
chip. The 2552 represents such an integration with
greatly enhanced features. The 2552 is fabricated with
an advanced CMOS process.
The 2552 is an upward solution that provides a dual
UART capability with 16 bytes of transmit and receive
FIFO memory, instead of none in the 16C450. The
2552 is designed to work with high speed modems and
shared network environments, that require fast data
processing time. Increased performance is realized in
the 2552 by the transmit and receive FIFOs. This
allows the external processor to handle more network-
ing tasks within a given time. For example, the
ST16C450 without a receive FIFO, will require un-
loading of the RHR in 93 microseconds (This example
uses a character length of 11 bits, including start/stop
bits at 115.2Kbps). This means the external CPU will
have to service the receive FIFO less than every 100
microseconds. However with the 16 byte FIFO in the
2552, the data buffer will not require unloading/load-
ing for 1.53 ms. This increases the service interval
giving the external CPU additional time for other
applications and reducing the overall UART interrupt
servicing time. In addition, the 4 selectable receive
FIFO trigger interrupt levels is uniquely provided for
maximum data throughput performance especially
when operating in a multi-channel environment. The
FIFO memory greatly reduces the bandwidth require-
ment of the external controlling CPU, increases per-
formance, and reduces power consumption.
The 2552 is capable of operation to 1.5 Mbps with a 24
MHz. With a crystal or external clock input of 7.3728
MHz the user can select data rates up to 460.8 Kbps.
The rich feature set of the 2552 is available through
internal registers. Selectable receive FIFO trigger
levels, selectable TX and RX baud rates, and modem
interface controls are all standard features. Following
a power on reset or an external reset, the 2552 is
software compatible with the previous generation,
ST16C550.
FUNCTIONAL DESCRIPTIONS
UART A-B Functions
The UART provides the user with the capability to Bi-
directionally transfer information between an external
CPU, the 2552 package, and an external serial de-
vice. A logic 0 on chip select pin -CS and a logic 1 on
CHSEL allows the user to configure, send data, and/
or receive data via UART channel A. A logic 0 on chip
select pin -CS and a logic 0 on CHSEL allows the user
to configure, send data, and/or receive data via UART
channel B. Individual channel select functions are
summarized in Table below.
CHIP SELECTs
Function
-CS = 1
-CS = 0
None
UART Channel selected as
follows:
CHSEL = 1
CHSEL = 0
UART CHANNEL A
UART CHANNEL B
During a write mode cycle, the setting of AFR bit-0 to
a logic 1 will override the CHSEL selection and allow
a simultaneous write to both UART channel sections.
This functional capability allow the registers in both
UART channels to be modified concurrently, saving
individual channel initialization time. Caution should
be considered however when using this capability.
Any in-process serial data transfer may be disrupted
by changing an active channels mode.
Internal Registers
The 2552 provides two sets of internal registers (A and
B) consisting of 12 registers each for monitoring and
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST16C2552_06 | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO |
| ST16C2552CJ | 制造商:EXAR 功能描述:IC , Dual UART 4MBPS 5.5 44 PLCC 制造商:Exar Corporation 功能描述: 制造商:XIC 功能描述: 制造商:Exar Corporation 功能描述:UART, 44 Pin, Plastic, PLCC |
| ST16C2552CJ-0A-EB | 功能描述:界面開發(fā)工具 Supports C2550 44 ld PLCC, ISA Interface RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評(píng)估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| ST16C2552CJ44 | 制造商:Exar Corporation 功能描述: 制造商:Exar Corporation 功能描述:UART, 44 Pin, Plastic, PLCC 制造商:EXER 功能描述:UART, 44 Pin, Plastic, PLCC 制造商:STAR 功能描述:UART, 44 Pin, Plastic, PLCC 制造商:STARTECH 功能描述:UART, 44 Pin, Plastic, PLCC |
| ST16C2552CJ44-F | 功能描述:UART 接口集成電路 2.97V-5.5V 16B FIFO temp 0C to 70C; UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
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