參數(shù)資料
型號(hào): ST16C2552
廠商: Exar Corporation
英文描述: Dual UART with 16-Byte Transmit and Receive FIFO(雙通用異步接收器/發(fā)送器(帶16字節(jié)接收和發(fā)送先進(jìn)先出))
中文描述: 雙UART),16字節(jié)的傳輸和接收FIFO(雙通用異步接收器/發(fā)送器(帶16字節(jié)接收和發(fā)送先進(jìn)先出)
文件頁(yè)數(shù): 3/32頁(yè)
文件大小: 409K
代理商: ST16C2552
ST16C2552
3
Rev. 3.50
Symbol
Pin
44
Signal
type
Pin Description
SYMBOL DESCRIPTION
A0
10
I
Address-0 Select Bit. - Internal register address selection.
A1
14
I
Address-1 Select Bit. - Internal register address selection.
A2
15
I
Address-2 Select Bit. - Internal register address selection.
CHSEL
16
I
Channel Select. - UART channel A or B is selected by the logical state of
this pin when the -CS is a logic 0. A logic 0 on CHSEL selects the UART
channel B while a logic 1 selects UART channel A.
-CS
18
I
Chip Select (active low) - This function selects channel, A or B, in
accordance with the logical state of the CHSEL pin. This allows data to be
transferred between the user CPU and the 2552 or the 2552 and the CPU
for a channel selected by CHSEL. Bit-0 of the MF Register overrides
CHSEL while in the write cycle mode, allowing the user to write both
channel registers simultaneously with one write cycle.
D0-D7
2-9
I/O
Data Bus (Bi-directional) - These pins are the eight bit, three statte data
bus for transferring information to or from the controlling external CPU. D0
is the least significant bit and the first data bit in a transmit or receive serial
data stream.
GND
12,22
Pwr
Signal and power ground.
INT A-B
34,17
O
Interrupt A, B (active high) - This function is associated with individual
channel interrupts, INT A-B. INT A-B are enabled when MCR bit-3 is set
to a logic 1, interrupts are enabled in the interrupt enable register (IER),
and when an interrupt condition exists. Interrupt conditions include:
receiver errors, available receiver buffer data, transmit buffer empty, or
when a modem status flag is detected.
-IOR
24
I
Read strobe. (active low ) - A logic 0 transition on this pin will load the
contents of an Internal register defined by address bits A0-A2 onto the
2552 data bus (D0-D7) for access by an external CPU.
-IOW
20
I
Write strobe. (active low) - A logic 0 transition on this pin will transfer the
contents of the data bus (D0-D7) from the external CPU to an internal
register that is defined by address bits A0-A2.
-MF A-B
35,19
O
Multi-Function A-B - This function is associated with an individual channel
function, A or B. User programmable bits 1-2 of the Alternate Function
Register (AFR), selects a signal function for output on these pins. -OP2
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