參數(shù)資料
型號(hào): ST16C2552
廠商: Exar Corporation
英文描述: Dual UART with 16-Byte Transmit and Receive FIFO(雙通用異步接收器/發(fā)送器(帶16字節(jié)接收和發(fā)送先進(jìn)先出))
中文描述: 雙UART),16字節(jié)的傳輸和接收FIFO(雙通用異步接收器/發(fā)送器(帶16字節(jié)接收和發(fā)送先進(jìn)先出)
文件頁數(shù): 11/32頁
文件大小: 409K
代理商: ST16C2552
ST16C2552
11
Rev. 3.50
DMA Operation
The 2552 FIFO trigger level provides additional flex-
ibility to the user for block mode operation. LSR bits 5-
6 provide an indication when the transmitter is empty
or has an empty location(s). The user can optionally
operate the transmit and receive FIFOs in the DMA
mode (FCR bit-3). When the transmit and receive
FIFOs are enabled and the DMA mode is deactivated
(DMA Mode 0), the 2552 activates the interrupt
output pin for each data transmit or receive operation.
When DMA mode is activated (DMA Mode 1), the
user takes the advantage of block mode operation by
loading or unloading the FIFO in a block sequence
determined by the receive trigger level and the trans-
mit FIFO. In this mode, the 2552 sets the interrupt
output pin when characters in the transmit FIFO is
below 16, or the characters in the receive FIFOs are
above the receive trigger level.
Loop-back Mode
The internal loop-back capability allows onboard diag-
nostics. In the loop-back mode the normal modem
interface pins are disconnected and reconfigured for
loop-back internally. MCR register bits 0-3 are used
for controlling loop-back diagnostic testing. In the
loop-back mode INT enable and MCR bit-2 in the MCR
register (bits 3/2) control the modem -RI and -CD
inputs respectively. MCR signals -DTR and -RTS (bits
0-1) are used to control the modem -CTS and -DSR
inputs respectively. The transmitter output (TX) and
the receiver input (RX) are disconnected from their
associated interface pins, and instead are connected
together internally (See Figure 4). The -CTS, -DSR, -
CD, and -RI are disconnected from their normal
modem control inputs pins, and instead are connected
internally to -DTR, -RTS, INT enable and MCR bit-2.
Loop-back test data is entered into the transmit hold-
ing register via the user data bus interface, D0-D7.
The transmit UART serializes the data and passes the
serial data to the receive UART via the internal loop-
back connection. The receive UART converts the
serial data back into parallel data that is then made
available at the user data interface, D0-D7. The user
optionally compares the received data to the initial
transmitted data for verifying error free operation of
the UART TX/RX circuits.
In this mode, the receiver and transmitter interrupts
are fully operational. The Modem Control Interrupts
are also operational. However, the interrupts can only
be read using lower four bits of the Modem Control
Register (MCR bits 0-3) instead of the four Modem
Status Register bits 4-7. The interrupts are still con-
trolled by the IER.
REGISTER FUNCTIONAL DESCRIPTIONS
The following table delineates the assigned bit func-
tions for the twelve 2552 internal registers. The as-
signed bit functions are more fully defined in the
following paragraphs.
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