參數(shù)資料
型號(hào): ST16C2552
廠商: Exar Corporation
英文描述: Dual UART with 16-Byte Transmit and Receive FIFO(雙通用異步接收器/發(fā)送器(帶16字節(jié)接收和發(fā)送先進(jìn)先出))
中文描述: 雙UART),16字節(jié)的傳輸和接收FIFO(雙通用異步接收器/發(fā)送器(帶16字節(jié)接收和發(fā)送先進(jìn)先出)
文件頁(yè)數(shù): 8/32頁(yè)
文件大?。?/td> 409K
代理商: ST16C2552
ST16C2552
8
Rev. 3.50
controlling the functions of each channel of the UART.
These resisters are shown in Table 3 below. The
UART registers function as data holding registers
(THR/RHR), interrupt status and control registers
(IER/ISR), a FIFO control register (FCR), line status
and control registers (LCR/LSR), modem status and
control registers (MCR/MSR), programmable data
rate (clock) control registers (DLL/DLM), a user as-
sessable scratchpad register (SPR), and an Alternate
Function Register (AFR).
Table 3, INTERNAL REGISTER DECODE
A2
A1
A0
READ MODE
WRITE MODE
General Register Set (THR/RHR, IER/ISR, MCR/MSR, LCR/LSR, SPR): Note 1*
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Receive Holding Register
Transmit Holding Register
Interrupt Enable Register
FIFO Control Register
Line Control Register
Modem Control Register
Interrupt Status Register
Line Status Register
Modem Status Register
Scratchpad Register
Scratchpad Register
Register Set Two (DLL/DLM/AFR): Note *2
0
0
0
0
0
1
0
1
0
LSB of Divisor Latch
MSB of Divisor Latch
Alternate Function Register
LSB of Divisor Latch
MSB of Divisor Latch
Alternate Function Register
Note 1* The General Register sets are accessible only when CS is a logic 0.
Note 2* The Baud Rate register and AFR register sets are accessible only when CS is a logic 0 and LCR bit-7 is
a logic 1 for the register set (A/B) being accessed.
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