參數(shù)資料
型號(hào)： ST16C2552
廠商： Exar Corporation
英文描述： Dual UART with 16-Byte Transmit and Receive FIFO(雙通用異步接收器/發(fā)送器（帶16字節(jié)接收和發(fā)送先進(jìn)先出）)
中文描述： 雙UART），16字節(jié)的傳輸和接收FIFO（雙通用異步接收器/發(fā)送器（帶16字節(jié)接收和發(fā)送先進(jìn)先出）
文件頁(yè)數(shù)： 20/32頁(yè)
文件大?。?/td> 409K
代理商： ST16C2552
ST16C2552
20
Rev. 3.50
MSR BIT-4:
During normal operation, this bit is the compliment of
the -CTS input. During the loop-back mode this bit is
equivalent to MCR bit-1 (-RTS).
MSR BIT-5:
During normal operation, this bit is the compliment of
the -DSR input. During the loop-back mode, this bit is
equivalent to MCR bit-0 (-DTR).
MSR BIT-6:
During normal operation, this bit is the compliment of
the -RI input. Reading this bit in the loop-back mode
produces the state of MCR bit-2 (-OP1).
MSR BIT-7:
During normal operation, this bit is the compliment of
the -CD input. Reading this bit in the loop-back mode
produces the state of MCR bit-3 (-OPA/B).
Note: Whenever any MSR bit 0-3: is set to logic 1, a
MODEM Status Interrupt will be generated.
Scratchpad Register (SPR)
The ST16C2552 provides a temporary data register to
store 8 bits of user information.
ALTERNATE FUNCTION REGISTER (AFR)
This is a read/write register used to select specific
modes of -MF operation and to allow both UART
registers sets to be written concurrently.
AFR BIT-0:
When this bit is set, CPU can write concurrently to the
same register in both UARTs. This function is intended
to reduce the dual UART initialization time. It can be
used by CPU when both channels are initialized to the
same state. The external CPU can set or clear this bit
by accessing either register set. When this bit is set the
channel select pin still selects the channel to be
accessed during read operation. Setting or clearing
this bit has no effect on read operations. The user
should ensure that LCR Bit-7 of both channels are in
the same state before executing a concurrent write to
the registers at address 0,1, or 2.
Logic 0 = No concurrent write. (normal default condi-
tion)
Logic 0 = Register set A and B are written concurrently
with a single external CPU I/O write operation.
AFR BIT-1-2:
Selects a signal function for output on the -MF A/B
pins. These signal functions are described as: -OP2
(interrupt enable), -BAUDOUT or -RXRDY. Only one
signal function can be selected at a time.
BIT-2
BIT-1
MF Function
0
0
1
1
0
1
0
1
-OP2
-BAUDOUT
-RXRDY
Reserved
AFR BIT 3-7:
Not used. All are initialized to logic 0.
ST16C2552 EXTERNAL RESET CONDITION
REGISTERS
RESET STATE
IER
ISR
LCR
MCR
LSR
IER BITS 0-7=0
ISR BIT-0=1, ISR BITS 1-7=0
LCR BITS 0-7=0
MCR BITS 0-7=0
LSR BITS 0-4=0,
LSR BITS 5-6=1 LSR, BIT 7=0
MSR BITS 0-3=0,
MSR BITS 4-7=input signals
FCR BITS 0-7=0
AFR BITS 0-7=0
MSR
FCR
MFR
SIGNALS
RESET STATE
TX
-OP2
-RTS
-DTR
INT
-TXRDY
High
High
High
High
Low
Low
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參數(shù)描述
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