
Parallel ports
ST10F252M
When a PORT2 line is used as a capture input, the state of the input latch, which represents
the state of the port pin, is directed to the CAPCOM unit via the line “Alternate Pin Data
Input”. If an external capture trigger signal is used, the direction of the respective pin is set
to input. If the direction is set to output, the state of the port output latch is read since the pin
represents the state of the output latch. This can be used to trigger a capture event through
software by setting or clearing the port latch. In the output configuration, no external device
may drive the pin, otherwise conflicts would occur.
When a PORT2 line is used as a compare output (compare modes 1 and 3), the compare
event (or the timer overflow in compare mode 3) directly effects the port output latch. In
compare mode 1, when a valid compare match occurs, the state of the port output latch is
read by the CAPCOM control hardware via the line “Alternate Latch Data Input”, inverted,
and written back to the latch via the line “Alternate Data Output”. The port output latch is
clocked by the signal “Compare Trigger” which is generated by the CAPCOM unit. In
compare mode 3, when a match occurs, the value '1' is written to the port output latch via
the line “Alternate Data Output”. When an overflow of the corresponding timer occurs, a '0' is
written to the port output latch. In both cases, the output latch is clocked by the signal
“Compare Trigger”. The direction of the pin is set to output by the user, otherwise the pin will
be in the high-impedance state and will not reflect the state of the output latch.
As can be seen from the port structure (
Figure 33), the user software always has free
access to the port pin even when it is used as a compare output. This is useful for setting up
the initial level of the pin when using compare mode 1 or the double-register mode. In these
modes, unlike in compare mode 3, the pin is not set to a specific value when a compare
match occurs but is toggled instead.
When the user software wants to write to the port pin at the same time a compare trigger
tries to clock the output latch, the write operation of the user software has priority. Each time
a CPU write access to the port output latch occurs, the input multiplexer of the port output
latch is switched to the line connected to the internal bus. The port output latch receives the
value from the internal bus and the hardware-triggered change is lost.
As all other capture inputs, the capture input function of pins P2.15...P2.0 can also be used
as external interrupt inputs (83.34 ns sample rate at 48 MHz CPU clock).
The upper eight PORT2 lines (P2.15 to P2.8) also can serve as fast external Interrupt inputs
(EX7IN to EX0IN).
P2.15 also serves as the input for CAPCOM2 timer T7 (T7IN).
Table 65 summarizes the alternate functions of PORT2.
Table 65.
PORT2 alternate functions
Pin
Alternate function a)
Alternate function b)
Alternate function c)
P2.2
CC2IO
P2.3
CC3IO
-
P2.4
CC4IO
-
P2.5
CC5IO
-
P2.6
CC6IO
-
P2.7
CC7IO
-
P2.8
CC8IO
EX0IN Fast Ext. Interrupt 0 Input -
P2.9
CC9IO
EX1IN Fast Ext. Interrupt 1 Input -