
Parallel ports
ST10F252M
An external 8-bit de-multiplexed bus only uses P0L, while P0H is free for I/O (provided that
no other bus mode is enabled).
PORT0 is also used to select the system start-up configuration. During reset, PORT0 is
configured to input and each line is held high through an internal pull-up device. Each line
can now be individually pulled to a low level (see the DC-level specifications in the
appropriate data sheets) through an external pull-down device. A default configuration is
selected when the respective PORT0 lines are at a high level. Through pulling individual
lines to a low level, this default can be changed according to the needs of the application.
The internal pull-up devices are designed such that an external pull-down resistors (see
Data Sheet specification) can be used to apply a correct low level. These external pull-down
resistors can remain connected to the PORT0 pins also during normal operation, however,
take care that they do not disturb the normal function of PORT0 (this may be the case, for
example, if the external resistor is too strong).
At the end of reset, the selected bus configuration is written to the BUSCON0 register. The
configuration of the high byte of PORT0, is copied into the special register RP0H. This read-
only register holds the selection for the number of chip selects and segment addresses.
Software can read this register to react to the selected configuration, if required. When the
reset is terminated, the internal pull-up devices are switched off, and PORT0 is switched to
the appropriate operating mode.
During external accesses in multiplexed bus modes, PORT0 first outputs the 16-bit intra-
segment address as an alternate output function. PORT0 is then switched to high-
impedance input mode to read the incoming instruction or data. In 8-bit data bus mode, two
memory cycles are required for word accesses, the first for the low byte and the second for
the high byte of the word. During write cycles PORT0 outputs the data byte or word after
outputting the address. During external accesses in de-multiplexed bus modes, PORT0
reads the incoming instruction or data word or outputs the data byte or word.
Figure 21.
PORT0 I/O and alternate functions
When an external bus mode is enabled, the direction of the port pin and the loading of data
into the port output latch are controlled by the bus controller hardware. The input of the port
output latch is disconnected from the internal bus and is switched to the line labeled
“Alternate Data Output” via a multiplexer. The alternate data can be the 16-bit intra-segment
address or the 8/16-bit data information. The incoming data on PORT0 is read on the line
“Alternate Data Input”. While an external bus mode is enabled, the user software should not
P0H.7
P0H.6
P0H.5
P0H.4/AN15
P0H.3/AN14
P0H.2/AN13
P0H.1/AN12
P0H.0/AN11
P0L.7/AN10
P0L.6
P0L.5
P0L.4
P0L.3
P0L.2
P0L.1
P0L.0
PORT0
P0H
P0L
Alternate Function
a)
b)
c)
d)
General Purpose
I/O and Analog Inputs
8-bit
Demux Bus
16-bit
Demux Bus
8-bit
MUX Bus
16-bit
MUX Bus
D7
D6
D5
D4
D3
D2
D1
D0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
A15
A14
A13
A12
A11
A10
A9
A8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0