
Memory organization
ST10F252M
memory interface, using the BUSCONx register corresponding to address matching
ADDRSELx register.
The XRAM2 address range is the one selected programming XADDR3 register, if XPEN (bit
2 in SYSCON register), and XRAM2EN (bit 3 of XPERCON register) are set. If bit XPEN is
cleared, then any access in the address range programmed for XRAM2 will be directed to
external memory interface, using the BUSCONx register corresponding to address
matching ADDRSELx register.
After reset, the XRAM2 address range is 09’0000h-09’3FFFh and is mirrored every
16 Kbyte boundary until 0F’FFFFh.
XRAM2 also represents the Stand-by RAM, which can be maintained biased through
EA/VSTBY pin when the main supply VDD is turned off.
As the XRAM appears like external memory, it cannot be used as system stack or as
register banks. The XRAM is not provided for single bit storage and therefore is not bit
addressable.
SFR/ESFR: 1024 bytes (2 x 512 bytes) of address space is reserved for the special function
register areas. SFRs are Wordwide registers which are used to control and to monitor the
function of the different on-chip units.
CAN1: Address range 00’EF00h - 00’EFFFh is reserved for the CAN1 module access. The
CAN1 is enabled by setting XPEN bit 2 of the SYSCON register and by setting CAN1EN bit
0 of the XPERCON register. Accesses to the CAN1 module use demultiplexed addresses
and a 16-bit data bus (only word accesses are possible). Two wait states give an access
time of 100 ns at 40 MHz CPU clock. No tristate waitstate is used.
CAN2: Address range 00’EE00h - 00’EEFFh is reserved for the CAN2 module access. The
CAN2 is enabled by setting XPEN bit 2 of the SYSCON register and by setting CAN2EN bit
1 of the XPERCON register. Accesses to the CAN2 module use demultiplexed addresses
and a 16-bit data bus (only word accesses are possible). Two wait states give an access
time of 100.0 ns at 40 MHz CPU clock. No tristate waitstate is used.
Note:
If one or the two CAN modules are used, Port 4 cannot be programmed to output all eight
segment address lines. Thus, only four segment address lines can be used, reducing the
external memory space to 5 Mbytes (1 Mbyte per CS line).
XRTC: Address range 00’ED00h - 00’EDFFh is reserved for the XRTC module access. The
XRTC is enabled by setting XPEN bit 2 of the SYSCON register and bit 4 of the XPERCON
register. Accesses to the XRTC module use demultiplexed addresses and a 16-bit data bus
(only word accesses are possible). Two wait states give an access time of 100.0 ns at
40 MHz CPU clock. No tristate waitstate is used.
XPWM: Address range 00’EC00h - 00’ECFFh is reserved for the XPWM module access.
The XPWM is enabled by setting XPEN bit 2 of the SYSCON register and bit 6 of the
XPERCON register. Accesses to the XPWM module use demultiplexed addresses and a 16-
bit data bus (only word accesses are possible). Two waitstates give an access time of
100.0 ns at 40 MHz CPU clock. No tristate waitstate is used. Only word access is allowed.
XASC: Address range 00’E900h - 00’E9FFh is reserved for the XASC module access. The
XASC is enabled by setting XPEN bit 2 of the SYSCON register and bit 7 of the XPERCON
register. Accesses to the XASC module use demultiplexed addresses and a 16-bit data bus
(only word accesses are possible). Two waitstates give an access time of 100.0 ns at
40 MHz CPU clock. No tristate waitstate is used.