MOTOROLA
Appendix - B Programmer’s Sheets
B-87
Preliminary
Application:
Date:
Programmer:
Sheet
B
5 of 11
TMR Status/Control Register (SCR) continued
TMR
TMR Status/Control
Register (SCR)
$1FFE80 + $7, $F, $17,
$1F
Bits
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
TCF TCFIE TOF TOFOE IEF IEFIE
IPS
INPUT
CM MSTR EEOF VAL
0
OPS OEN
Write
FORCE
RESET
000
0
00
0
00
0
denotes Reserved Bits
Bits
Name
Description
7 - 6
CAPTURE MODE
Input Capture Mode
These bits specify the operation of the Capture register and the operation of the input edge flag.
00
Capture function is disabled
01
Load Capture register on rising edge of input
10
Load Capture register on falling edge of input
11
Load Capture register on any edge of input
5
MSTR
Master Mode
When set, this bit enables Compare function’s output to be broadcasted to the other
counter/timers in the module. This signal can then be used to reinitialize the other counters and/or
force their OFLAG signal outputs.
4
EEOF
Enable External OFLAG Force
When set, this bit enables the Compare from another counter/timer within the same module to
force the state of this counter’s OFLAG output signal.
3
VAL
Forced OFLAG Value
This bit determines the value of the OFLAG output signal when a software triggered FORCE
command, or another counter/timer set as a master, issues a FORCE command.
2
FORCE
Force OFLAG Output
This write-only bit forces the current value of the VAL bit to be written to the OFLAG output. This
bit is read as 0. The VAL and FORCE bits can be written simultaneously in a single write
operation. Write to the FORCE bit only when the counter is disabled.
0
No action
1
Forces the current value of the Val bit to be written to OFLAG output
1
OPS
Output Polarity Select
This bit determines the polarity of the OFLAG output signal.
0
True polarity
1
Inverted polarity
0
OEN
Output Enable
When set, this bit enables the OFLAG output signal to be placed on the external pin. Setting this
bit connects a timer’s output pin to its input. Polarity of the signal will be determined by OPS bit.
TMRA0_SCR (Timer A, Channel 0 Status/Control)—Address: TMRA_BASE + $7
TMRA1_SCR (Timer A, Channel 1 Status/Control)—Address: TMRA_BASE + $F
TMRA2_SCR (Timer A, Channel 2 Status/Control)—Address: TMRA_BASE + $17
TMRA3_SCR (Timer A, Channel 3 Status/Control)—Address: TMRA_BASE + $1F