參數(shù)資料
型號： SPAK302PV16VC
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144
封裝： 20 X 20 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, PLASITC, LQFP-144
文件頁數(shù)： 45/128頁
文件大?。?/td> 641K
代理商： SPAK302PV16VC
MC68EN302 Module Bus Controller
2-6
MC68EN302 REFERENCE MANUAL
MOTOROLA
2.7 PARITY CONTROL AND STATUS REGISTER (PCSR)
This register controls and gives the status of the parity checking portions of the parity
circuitry. This register is set to 0x0000 upon hardware reset.
PIE—Parity Error Interrupt Enable. This bit determines if an interrupt is generated when a
parity error is detected.
0 = No interrupt is generated.
1 = Either a level 3 or level 5 interrupt is generated, depending upon the encoding of
the MIL bit in the IER register.
OPAR—Odd Parity. This bit is used to determine if odd or even parity is used.
0 = Parity is even.
1 = Parity is odd.
PEC—Parity Error Chip Selects (PEC3–PEC0). These status bits indicate that there was a
parity error in the corresponding Chip Select Bank. If one of the three bits is set to one, a
parity error is detected in the corresponding bank. If the PIE bit is set, a level 5 (or 3) interrupt
is driven to the processor as long as one of the PEC3–PEC0 bits are set. PEC3–PEC0 are
sticky bits which are cleared when a one is written to them or upon hardware reset. Writing
a zero does not change the value of the PEC bits. The PARITYE pin is asserted until the
PEC3–PEC0 bits are all cleared.
NOTE
If the Parity Pin Enable bit (PPE in MBC CSR) = 0 and parity is
enabled with CSPE in CSER3–CSER0, then a parity error will be
reported on the associated PEC bit.
PED—Parity Error DRAM (PED1–PED0). These status bits indicate that there was a parity
error in the corresponding DRAM bank. If one of the two bits is set to one, a parity error is
detected in the corresponding bank. If the PIE bit is set, a level 5 (or 3) interrupt is driven to
the processor as long as one of the PED bits is set. PED are sticky bits which are cleared
when a one is written to them or upon hardware reset. Writing a zero does not change the
value of the PED bits. Writing a zero does not change the value of the PED bits. The
PARITYE pin is asserted as long as a PED bit is set.
NOTE
If the Parity Pin Enable bit (PPE in MBC CSR) = 0 and parity is
enabled on the DRAM interface (PE1 and/or PE0 = 1 in DCR)
then a parity error will be reported on PED1–PED0.
PIV—Parity Error Interrupt Vector (PIV7–PIV0). If the PIE bit is set, a parity error generates
a level 5 (or 3) interrupt. The PIV bits determine what interrupt vector is returned in response
to a level 5 (or 3) parity error interrupt.
15
14
13
12
11
10
9876543210
PIE
OPAR PEC3 PEC2 PEC1 PEC0 PED1 PED0
PIV7
PIV6
PIV5
PIV4
PIV3
PIV2
PIV1
PIV0
相關(guān)PDF資料
PDF描述
SPAK302FC25C 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP132
MC68EN360EM25 7 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP240
MC68EN360FE33 RISC MICROCONTROLLER, CQFP240
MC68360RC25 RISC MICROCONTROLLER, CPGA241
MC68EN360RC25 RISC MICROCONTROLLER, CPGA241
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SPAK56854FG120 制造商:Freescale Semiconductor 功能描述:
SPAK56857BU120 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:120 MIPS Hybrid Processor
SPAK56F803BU80 制造商:Freescale Semiconductor 功能描述:
SPAK56F805FV80 制造商:Freescale Semiconductor 功能描述:
SPAKDSP303AG100 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC SPAKDSP303AG100 RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報(bào)價(jià)

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*