參數(shù)資料
型號: SPAK302PV16VC
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144
封裝: 20 X 20 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, PLASITC, LQFP-144
文件頁數(shù): 116/128頁
文件大小: 641K
代理商: SPAK302PV16VC
IEEE 1149.1 (JTAG) Test Access Port
MOTOROLA
7-3
Figure 7-2. TAP Controller State Machine
7.3 BOUNDARY SCAN REGISTER
The MC68EN302 IEEE 1149.1 implementation has a 163-bit boundary scan register. This
register contains bits for all device signal pins and associated control signals with the follow-
ing exceptions. The FRZ and IAC signals which are not pinned out on the TQFP package
are not included in the scan chain. The XTAL pin is associated with an analog signal and is
not included in the boundary scan register. The EXTAL pin (clock in) is not included to min-
imize loading on this signal, however a boundary scan cell is included for an internal signal,
SCLK which is the clock input to the MBC, Ethernet and DRAM controller logic.
TEST LOGIC
RESET
RUN-TEST/IDLE
SELECT-DR_SCAN
CAPTURE-DR
SHIFT-DR
EXIT1-DR
PAUSE-DR
EXIT2-DR
UPDATE-DR
SELECT-IR_SCAN
CAPTURE-IR
SHIFT-IR
EXIT1-IR
PAUSE-IR
EXIT2-IR
UPDATE-IR
0
1
0
1
0
1
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