參數(shù)資料
型號(hào)： SN54ABT18502HVR
廠商： TEXAS INSTRUMENTS INC
元件分類： 總線收發(fā)器
英文描述： ABT SERIES, DUAL 9-BIT BOUNDARY SCAN REG TRANSCEIVER, TRUE OUTPUT, CQFP68
封裝： CERAMIC, QFP-68
文件頁(yè)數(shù)： 7/30頁(yè)
文件大?。?/td> 451K
代理商： SN54ABT18502HVR
SN54ABT18502, SN74ABT18502
SCAN TEST DEVICES WITH
18-BIT REGISTERED BUS TRANSCEIVERS
SCBS109B – AUGUST 1992 – REVISED JUNE 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
15
boundary-control register opcode description (continued)
sample inputs/toggle outputs (TOPSIP)
Data appearing at the selected device input pins is captured in the shift-register elements of the selected BSCs
on each rising edge of TCK. This data is then updated in the shadow latches of the selected input BSCs and
applied to the inputs of the normal on-chip logic. Data in the shift-register elements of the selected output BSCs
is toggled on each rising edge of TCK and is then updated in the shadow latches and applied to the associated
device output pins on each falling edge of TCK.
pseudo-random pattern generation (PRPG)
A pseudo-random pattern is generated in the shift-register elements of the selected BSCs on each rising edge
of TCK, updated in the shadow latches, and applied to the associated device output pins on each falling edge
of TCK. This data is also updated in the shadow latches of the selected input BSCs and applied to the inputs
of the normal on-chip logic. Figures 4 and 5 illustrate the 36-bit linear-feedback shift-register algorithms through
which the patterns are generated. An initial seed value should be scanned into the boundary-scan register prior
to performing this operation. A seed value of all zeroes will not produce additional patterns.
=
1B8-O
1B7-O
1B6-O
1B5-O
1B4-O
1B3-O
1B2-O
1B1-O
1B9-O
1A7-I
1A6-I
1A5-I
1A4-I
1A3-I
1A2-I
1A1-I
1A8-I
1A9-I
2A7-I
2A6-I
2A5-I
2A4-I
2A3-I
2A2-I
2A1-I
2A8-I
2A9-I
2B8-O
2B7-O
2B6-O
2B5-O
2B4-O
2B3-O
2B2-O
2B1-O
2B9-O
Figure 4. 36-Bit PRPG Configuration (1OEAB = 2OEAB = 0, 1OEBA = 2OEBA = 1)
相關(guān)PDF資料
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