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參數(shù)資料
| 型號(hào)： | SN54ABT18502HVR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | ABT SERIES, DUAL 9-BIT BOUNDARY SCAN REG TRANSCEIVER, TRUE OUTPUT, CQFP68 |
| 封裝： | CERAMIC, QFP-68 |
| 文件頁數(shù)： | 20/30頁 |
| 文件大?。?/td> | 451K |
| 代理商： | SN54ABT18502HVR |
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SN54ABT18502, SN74ABT18502
SCAN TEST DEVICES WITH
18-BIT REGISTERED BUS TRANSCEIVERS
SCBS109B – AUGUST 1992 – REVISED JUNE 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
27
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (normal mode) (see Figure 13)
SN54ABT18502
SN74ABT18502
UNIT
MIN
MAX
MIN
MAX
UNIT
fclock
Clock frequency
CLKAB or CLKBA
0
100
0
100
MHz
t
Pulse duration
CLKAB or CLKBA high or low
3.5
ns
tw
Pulse duration
LEAB or LEBA high
3.5
ns
A before CLKAB
↑ or B before CLKBA↑
4
tsu
Setup time
A before LEAB
↓ or B before LEBA↓
CLK high
3.5
ns
A before LEAB
↓ or B before LEBA↓
CLK low
2
th
Hold time
A after CLKAB
↑ or B after CLKBA↑
0
ns
th
Hold time
A after LEAB
↓ or B after LEBA↓
2
ns
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (test mode) (see Figure 13)123
SN54ABT18502
SN74ABT18502
UNIT
MIN
MAX
MIN
MAX
UNIT
fclock
Clock frequency
TCK
0
50
0
50
MHz
tw
Pulse duration
TCK high or low
8
ns
A, B, CLK, LE, or OE before TCK
↑
4.5
tsu
Setup time
TDI before TCK
↑
7.5
ns
TMS before TCK
↑
3
A, B, CLK, LE, or OE after TCK
↑
0.5
th
Hold time
TDI after TCK
↑
0.5
ns
TMS after TCK
↑
0.5
td
Delay time
Power up to TCK
↑
50
ns
tr
Rise time
VCC power up
1
s
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
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