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參數(shù)資料
| 型號： | SN54ABT18502HVR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | ABT SERIES, DUAL 9-BIT BOUNDARY SCAN REG TRANSCEIVER, TRUE OUTPUT, CQFP68 |
| 封裝： | CERAMIC, QFP-68 |
| 文件頁數(shù)： | 14/30頁 |
| 文件大?。?/td> | 451K |
| 代理商： | SN54ABT18502HVR |
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SN54ABT18502, SN74ABT18502
SCAN TEST DEVICES WITH
18-BIT REGISTERED BUS TRANSCEIVERS
SCBS109B – AUGUST 1992 – REVISED JUNE 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
21
boundary-control register opcode description (continued)
simultaneous PSA and binary count up (PSA/COUNT)
Data appearing at the selected device input pins is compressed into an 18-bit parallel signature in the
shift-register elements of the selected input BSCs on each rising edge of TCK. This data is updated in the
shadow latches of the selected input BSCs andapplied to the inputs of the normal on-chip logic. At the same
time, an 18-bit binary count-up pattern is generated in the shift-register elements of the selected output BSCs
on each rising edge of TCK, updated in the shadow latches, and applied to the associated device output pins
on each falling edge of TCK. Figures 10 and 11 illustrate the 18-bit linear-feedback shift–register algorithms
through which the signature is generated. An initial seed value should be scanned into the boundary-scan
register prior to performing this operation.
=
MASKX.X
1B8-O
1B7-O
1B6-O
1B5-O
1B4-O
1B3-O
1B2-O
1B1-O
1B9-O
1A7-I
1A6-I
1A5-I
1A4-I
1A3-I
1A2-I
1A1-I
1A8-I
1A9-I
2A7-I
2A6-I
2A5-I
2A4-I
2A3-I
2A2-I
2A1-I
2A8-I
2A9-I
2B8-O
2B7-O
2B6-O
2B5-O
2B4-O
2B3-O
2B2-O
2B1-O
2B9-O
=
MSB
LSB
Figure 10. 18-Bit PSA/COUNT Configuration (1OEAB = 2OEAB = 0, 1OEBA = 2OEBA = 1)
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