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參數(shù)資料
| 型號(hào)： | SN54ABT18502HVR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | ABT SERIES, DUAL 9-BIT BOUNDARY SCAN REG TRANSCEIVER, TRUE OUTPUT, CQFP68 |
| 封裝： | CERAMIC, QFP-68 |
| 文件頁數(shù)： | 6/30頁 |
| 文件大?。?/td> | 451K |
| 代理商： | SN54ABT18502HVR |
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SN54ABT18502, SN74ABT18502
SCAN TEST DEVICES WITH
18-BIT REGISTERED BUS TRANSCEIVERS
SCBS109B – AUGUST 1992 – REVISED JUNE 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
14
instruction register opcode description (continued)
boundary toggle outputs
The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during
Capture-DR. Data in the shift-register elements of the selected output BSCs is toggled on each rising edge of
TCK in Run-Test/Idle, updated in the shadow latches, and applied to the associated device output pins on each
falling edge of TCK in Run-Test/Idle. Data in the selected input BSCs remains constant and is applied to the
inputs of the normal on-chip logic. Data appearing at the device input pins is not captured in the input BSCs.
The device operates in the test mode.
boundary-control register scan
The boundary-control register is selected in the scan path. The value in the boundary-control register remains
unchanged during Capture-DR. This operation must be performed prior to a boundary run test operation in order
to specify which test operation is to be executed.
Table 5. Boundary-Control Register Opcodes
BINARY CODE
BIT 2
→ BIT 0
MSB
→ LSB
DESCRIPTION
X00
Sample inputs/toggle outputs (TOPSIP)
X01
Pseudo-random pattern generation/36-bit mode (PRPG)
X10
Parallel signature analysis/36-bit mode (PSA)
011
Simultaneous PSA and PRPG/18-bit mode (PSA/PRPG)
111
Simultaneous PSA and binary count up/18-bit mode (PSA/COUNT)
boundary-control register opcode description
The boundary-control register opcodes are decoded from BCR bits 2 – 0 as shown in Table 5. The selected test
operation is performed while the RUNT instruction is executed in the Run-Test/Idle state. The following
descriptions detail the operation of each BCR instruction and illustrate the associated PSA and PRPG
algorithms.
In general, while the control input BSCs (bits 83 – 72) are not included in the toggle, PSA, PRPG, or COUNT
algorithms, the output-enable BSCs (bits 83– 80 of the BSR) control the drive state (active or high-impedance)
of the selected device output pins. These BCR instructions are only valid when both bytes of the device are
operating in one direction of data flow (that is, 1OEAB
≠ 1OEBA and 2OEAB ≠ 2OEBA) and in the same direction
of data flow (that is, 1OEAB
= 2OEAB and 1OEBA = 2OEBA). Otherwise, the bypass instruction is operated.
PSA input masking
Bits 20 – 3 of the boundary-control register are used to specify device input pins to be masked from PSA
operations. Bit 20 selects masking for device input pin 2A9 during A-to-B data flow or for device input pin 2B9
during B-to-A data flow. Bit 3 selects masking for device input pins 1A1 or 1B1 during A-to-B or B-to-A data flow,
respectively. Bits intermediate to 20 and 3 mask corresponding device input pins in order from most significant
to least significant, as indicated in Table 2. When the mask bit which corresponds to a particular device input
has a logic 1 value, the device input pin is masked from any PSA operation, meaning that the state of the device
input pin is ignored and has no effect on the generated signature. Otherwise, when a mask bit has a logic 0 value,
the corresponding device input is not masked from the PSA operation.
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