參數(shù)資料
型號(hào)： SN54ABT18502HVR
廠商： TEXAS INSTRUMENTS INC
元件分類： 總線收發(fā)器
英文描述： ABT SERIES, DUAL 9-BIT BOUNDARY SCAN REG TRANSCEIVER, TRUE OUTPUT, CQFP68
封裝： CERAMIC, QFP-68
文件頁(yè)數(shù)： 27/30頁(yè)
文件大?。?/td> 451K
代理商： SN54ABT18502HVR
SN54ABT18502, SN74ABT18502
SCAN TEST DEVICES WITH
18-BIT REGISTERED BUS TRANSCEIVERS
SCBS109B – AUGUST 1992 – REVISED JUNE 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
6
test architecture
Serial test information is conveyed by means of a 4-wire test bus or test access port (TAP), that conforms to IEEE
Standard 1149.1-1990. Test instructions, test data, and test control signals are all passed along this serial test
bus. The TAP controller monitors two signals from the test bus, namely TCK and TMS. The function of the TAP
controller is to extract the synchronization (TCK) and state control (TMS) signals from the test bus and generate
the appropriate on-chip control signals for the test structures in the device. Figure 1 shows the TAP controller
state diagram.
The TAP controller is fully synchronous to the TCK signal. Input data is captured on the rising edge of TCK and
output data changes on the falling edge of TCK. This scheme ensures that data to be captured is valid for fully
one-half of the TCK cycle.
The functional block diagram illustrates the IEEE Standard 1149.1-1990 4-wire test bus and boundary-scan
architecture and the relationship between the test bus, the TAP controller, and the test registers. As illustrated,
the device contains an 8-bit instruction register and four test data registers: an 84-bit boundary-scan register,
a 21-bit boundary-control register, a 1-bit bypass register, and a 32-bit device identification register.
Test-Logic-Reset
Run-Test/Idle
Select-DR-Scan
Capture-DR
Shift-DR
Exit1-DR
Pause-DR
Update-DR
TMS = L
TMS = H
TMS = L
TMS = H
TMS = L
TMS = H
TMS = L
TMS = H
TMS = L
Exit2-DR
Select-IR-Scan
Capture-IR
Shift-IR
Exit1-IR
Pause-IR
Update-IR
TMS = L
TMS = H
TMS = L
TMS = H
TMS = L
TMS = H
TMS = L
Exit2-IR
TMS = L
TMS = H
TMS = L
TMS = H
TMS = L
TMS = H
TMS = L
Figure 1. TAP Controller State Diagram
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