參數(shù)資料
型號(hào)： SIS300
廠商： SILICON INTEGRATED SYSTEMS CORP
元件分類： 圖形處理器
英文描述： GRAPHICS PROCESSOR, PBGA365
封裝： 27 X 27 MM, BGA-365
文件頁數(shù)： 99/115頁
文件大小： 2426K
代理商： SIS300
SiS300 2D/3D/Video/DVD Accelerator
Preliminary V0.3 March 23, 1999
76
Silicon Integrated Systems Corporation
63h
MPEG Auto-Flipping Control Read-Back Register 3
64h
MPEG Auto-Flipping Field Display Vertical Scaling
Factor Fraction Low Register
65h
MPEG Auto-Flipping Field Display Vertical Scaling
Factor Fraction High Register
5.11
DIGITAL VIDEO INTERFACE REGISTER
Register Type: Read/Write
Read/Write Port:
RIO+04
Default:
00h
D[5:0]
Digital Video Interface Register Index Bit[7:0] (00h ~ 28h)
Table 5.11-1 Table of digital video interface registers
INDEX (RIO+04)
DIGITAL VIDEO INTERFACE REGISTER (RIO+05)
00h
Function Control Register
01h
Mode Selection and FIFO Threshold High
02h
Mode Selection, PCI Bus Clock and FIFO Threshold Low
03h
FIFO Stop Operation
04h
Access Memory Starting Address High
05h
Access Memory Starting Address Median
06h
Access Memory Starting Address Low
07h
Access Memory Line Offset
08h
CRT2 Horizontal Total
09h
Overflow Register
0Ah
CRT2 Horizontal Display Enable End
0Bh
CRT2 Horizontal Retrace Start
0Ch
Overflow Register
0Dh
CRT2 Horizontal Retrace End
0Eh
CRT2 Vertical Total
0Fh
CRT2 Vertical Display Enable End
10h
CRT2 Vertical Retrace Start
11h
CRT2 Vertical Retrace End and Enable CRC Check and
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