參數(shù)資料
型號： SIS300
廠商： SILICON INTEGRATED SYSTEMS CORP
元件分類： 圖形處理器
英文描述： GRAPHICS PROCESSOR, PBGA365
封裝： 27 X 27 MM, BGA-365
文件頁數(shù)： 56/115頁
文件大小： 2426K
代理商： SIS300
SiS300 2D/3D/Video/DVD Accelerator
Preliminary V0.3 March 23, 1999
37
Silicon Integrated Systems Corporation
this agent desires the use of the bus.
E2
REQ#
I/O
PCI Master Grant indicates to the agent that
accesses to the bus has been granted.
F2, F3, E1
ST[2:0]
I
AGP Status bus provides information from the
arbiter to a Master on what it may do.
F1
RBF#
I
AGP Read Buffer Full indicates if the master is
ready to accept previously requested low priority
read data or not.
G5
WBF#
I/O
Reserved for AGP 4X, IDSEL muxed with WBF
L2, U2
AD_STB[1:0]
I
AGP AD Bus Strobe provides timing for 2x data
transfer mode on the AD[15:0] and AD[31:16].
K4, R5
AD_STB#[1:0]
I
Reserved for AGP 4X
H2
SB_STB
I/O
AGP STB bus strobe provides timing for 2x data
transfer mode on the SBA[7:0]
H5
SB_STB#
I/O
Reserved for AGP 4X
H3, J1, H4,
H1, G3, G1,
G4, G2
SBA[7:0]
I/O
AGP Sideband bus.
T5
AGPVREF
Reference
Voltage
for
AGP
AD[31:0]
and
AD_STB[1:0] I/O pads.
DRAM Bus
BALL NO.
SIGNAL
NAME
TYPE
DESCRIPTION
F17, P18,
U12, V6
SCLK[3:0]
I/O
Clock output
**
DQ[127:0]
I/O
Memory data bus
C17, F20,
F16, C18,
J18, P20,
N17, K18,
U16, Y10,
DQM#[15:0]
I/O
Memory byte input/output mask
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