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| 型號： | SIS300 |
| 廠商： | SILICON INTEGRATED SYSTEMS CORP |
| 元件分類： | 圖形處理器 |
| 英文描述： | GRAPHICS PROCESSOR, PBGA365 |
| 封裝： | 27 X 27 MM, BGA-365 |
| 文件頁數(shù)： | 55/115頁 |
| 文件大?。?/td> | 2426K |
| 代理商： | SIS300 |
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SiS300 2D/3D/Video/DVD Accelerator
Preliminary V0.3 March 23, 1999
36
Silicon Integrated Systems Corporation
4
SiS300 PIN LIST AND ASSIGNMENT
AGP/PCI Bus
BALL NO.
SIGNAL
NAME
TYPE
DESCRIPTION
B1
RST#
I
PCI Reset is used to bring PCI-specific registers,
sequencer, and signals to a consistent state.
E3
BCLK
I
PCI
Bus
Clock
provides
timing
for
all
transactions on PCI bus.
**
AD[31:0]
I/O
PCI Address/Data Bus are multiplexed on the
same pins. The Address phase is the clock cycle
in which FRAME* is asserted and the data phase
immediately follows the address phase.
K5, N2, R1,
R4
C/BE#[3:0]
I/O
PCI Command/Byte Enable Bus are multiplexed
on the same pins. During the address phase of a
transaction, C/BE define the bus command, and
during the data phase C/BE are used as Byte
Enables.
N5
PAR
I/O
PCI Parity Bit is even parity across AD[31:0] and
C/BE[3:0].
M5
FRAME#
I/O
PCI Frame Cycle is driven by the current master
to indicate the beginning and duration of an
access.
N3
TRDY#
I/O
PCI Target Ready indicates the target agent's
(selected device's) ability to complete the current
data phase of the transaction.
P1
IRDY#
I/O
PCI Initiator Ready indicates the initiating agent's
(bus master's) ability to complete the current
data phase of the transaction
N4
STOP#
I/O
PCI
Stop
indicates
the
current
target
is
requesting the master to stop the current
transaction.
P2
DEVSEL#
I/O
PCI Initialization Device Select is used as a chip
select
during
configuration
read
and
write
transactions.
E4
INTA#
I/O
PCI
Interrupt
indicates
the
interrupt
signal
generated by SiS300.
F5
GNT#
I
PCI Master Request indicates to the arbiter that
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