- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄98080 > SII3114CT176 PCI BUS CONTROLLER, PQFP176 PDF資料下載
參數(shù)資料
| 型號(hào)： | SII3114CT176 |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PQFP176 |
| 封裝： | TQFP-176 |
| 文件頁(yè)數(shù)： | 92/127頁(yè) |
| 文件大?。?/td> | 564K |
| 代理商： | SII3114CT176 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)當(dāng)前第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)
SiI3114 PCI to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
2007 Silicon Image, Inc.
59
SiI-DS-0103-D
Bit [31:28]: Reserved (R). This bit field is reserved and returns zeros on a read.
Bit [27]: Memory Init Done (R) – This bit set indicates that the memory initialization sequence is done. The
memory sequence is activated upon the release of reset.
Bit [26]: Mem Init (R) – Memory Initialized. This bit set indicates that the memory was initialized properly (a
correct data sequence was read from the Flash.)
Bit [25]: Mem Access Start (R/W) – Memory Access Start. This bit is set to initiate an operation to Flash
memory. This bit is cleared when the operation is complete.
Bit [24]: Mem Access Type (R/W) – Memory Access Type. This bit is set to define a read operation from
Flash memory. This bit is cleared to define a write operation to Flash memory.
Bit [23:19]: Reserved (R). This bit field is reserved and returns zeros on a read.
Bit [18:00]: Memory Address (R/W). This bit field is programmed with the address for a flash memory read
or write access.
Flash Memory Data
Address Offset: 54H
Access Type: Read/Write
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
GPIO Control
Memory Data
This register defines the data register for the Flash memory and GPIO interface in the SiI3114. The system writes
to this register for a write operation to Flash memory, and reads from this register on a read operation from Flash
memory. The GPIO Control bits control operation of the Flash data lines for use as General Purpose I/O. GPIO is
only enabled when the GPIOEN pin is pulled high.
Bit [31:16]: Reserved (R). This bit field is reserved and returns zeros on a read.
Bit [15:08]: GPIO Control – The bits of this field are written to control the output type for corresponding
Flash data lines; if a bit is a 1 the corresponding output is an open drain output (only driven low); if a 0 the
corresponding output is always driven. The bits of this field, when read, report signal transition detection on
the corresponding Flash data input; reading the register resets the transition detect bits.
Bit [07:00]: Memory Data (R/W) – Flash Memory Data. This bit field is used for Flash write data on a write
operation, and returns the Flash read data on a read operation.
This register defines the data register for the Flash memory and GPIO interface in the Taurus. The GPIO Control
bits control operation of the Flash data lines for use as General Purpose I/O. GPIO is enabled when the GPIOEN
pin is pulled high.
EEPROM Memory Address – Command + Status
Address Offset: 58H
Access Type: Read/Write
Reset Value: 0x0800_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
Mem
Error
M
e
m
Init
Done
M
e
m
Init
M
e
m
A
ccess
St
art
M
e
m
A
c
cess
Type
Reserved
Mem Address
This register defines the address and command/status register for EEPROM memory interface in the SiI3114.
The register bits are defined below.
Bit [31:29]: Reserved (R). This bit field is reserved and returns zeros on a read.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SII3114CTU | PCI BUS CONTROLLER, PQFP176 |
| SII3124ACBHU | PCI BUS CONTROLLER, PBGA364 |
| SII3512ECTU128 | PCI BUS CONTROLLER, PQFP128 |
| SII3531ACNU | PCI BUS CONTROLLER, QCC48 |
| SIO10N268-NU | MULTIFUNCTION PERIPHERAL, PQFP128 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SII3114CTU | 制造商:Silicon Image Inc 功能描述:PCI to Serial ATA Controller 176-Pin TQFP 制造商:SILICON 功能描述: |
| SII3124A | 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:PCI-X to Serial ATA Controller |
| SII3124ACBHU | 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:PCI-X to Serial ATA Controller |
| SII3132 | 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:PCI Express to 2-Port Serial ATA II Host Controller |
| SII3132CNU | 制造商:Silicon Image Inc 功能描述:PCI Express to Serial ATA Controller 88-Pin QFN |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。