- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄98080 > SII3114CT176 PCI BUS CONTROLLER, PQFP176 PDF資料下載
參數(shù)資料
| 型號(hào)： | SII3114CT176 |
| 元件分類(lèi)： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PQFP176 |
| 封裝： | TQFP-176 |
| 文件頁(yè)數(shù)： | 105/127頁(yè) |
| 文件大?。?/td> | 564K |
| 代理商： | SII3114CT176 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)當(dāng)前第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)
SiI3114 PCI to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
2007 Silicon Image, Inc.
71
SiI-DS-0103-D
Bit [20]: Cont_dis (R/W)– Setting this bit disables the CONT primitive, i.e., the SiI3114 will always send the
actual primitive instead of a CONT followed by random data.
Bit [19]: VS_Lock_Abort (R/W)– This bit controls the changes to the entries in the Command Protocol
Table upon receiving a VS_Lock command. If this bit is set, all Command Protocol Table will be cleared. If
this bit is not set, the Command Protocol Table will not be cleared in the VS_Lock state.
Bit [18]: fpdmawr (W)– Setting this bit initiates a DMA write transfer
Bit [17]: dmainen(R/W)– This bit enables Read DMA operations for First Party DMA or transparent FIS
operation.
Bit [16]: dmaouten (R/W)– This bit enables Write DMA operations for First Party DMA or transparent FIS
operation.
Bit [15]: Reserved (R/W). This bit is reserved and returns zero on a read. Always write 0 to these bits.
Bit [14]: devdrvn (R/W) – This bit enables the protocol to be solely determined by FISes from the device.
Bit [13]: nienfis_dis (R/W)– If this bit is set, a Control Register FIS will not be sent in response to a change
in nIEN.
Bit [12]: Reserved (W). Always write 0 to these bits.
Bit [11]: ComWake/Clear_BSY (R/W)– When the Serial ATA interface is in PARTIAL or SLUMBER mode,
setting this bit (to 1) asserts ComWake on the Serial ATA bus. When the Serial ATA interface is ON and an
interlocked FIS is received, setting this bit (to 1) clears BSY in the ATA Status.
Bit [10:09]: pm_fiscfg[1:0] (R/W)– Configuration for interpreting FISes with a different Port Multiplier port
number from that specified in SControl.
Bit [08]: pm_locken (R/W)– If set, no SYNC is sent after a DMA Activate FIS, a PIO Setup FIS for PIO Out,
or an interlocked FIS when dmaouten (bit 16) is set.
Bit [07]: regfismode (R/W) – If set, received Register FIS will not be used to update task file if BSY = DRQ
= 0.
Bit [06]: PMCHG (R/W1C)– This bit reports a change in the Power Management mode. This bit
corresponds to the interrupt enabled by bit 26 of SIEN. This bit is cleared by writing a 1.
Bit [05:04]: PMMODE (R)– These bits report the power management mode status: bit 5 corresponds to
Slumber mode; bit 4 to Partial mode. A transition on either of these bits causes a Power Management
mode change interrupt.
Bit [03:02]: Reserved (R). This bit field is reserved and returns zeros on a read.
Bit [01:00]: PMREQ (W) – These bits initiate power management requests: setting bit 1 will send a
Slumber mode request to the device; setting bit 0 will send a Partial mode request to the device.
Serial ATA PHY Configuration
Address Offset: 144H
Access Type: Read/Write
Reset Value: 0x2000_80B0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Reserved
B
y
pass
OOB
R
eserved
Tx_Swing_1
Reserved
Tx_Swing_0
Reserved
The PHY Configuration register is auto-initialized from external flash or EEPROM. The bit definitions are as
follows:
Bit[31:22]: Reserved. The values of these bits should not be changed from their defaults otherwise erratic
operation may result
Bit[21]: Bypass OOB sequence. If the bit set to 1, all channel Tx outputs random pattern data.
Bit[20]: Reserved. The value of this bits should not be changed from their defaults otherwise erratic
operation may result
Bit[19]: Tx_Swing_1: This bit, together with Tx_Swing_0, sets the nominal output amplitude for the
Transmitter
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SII3114CTU | PCI BUS CONTROLLER, PQFP176 |
| SII3124ACBHU | PCI BUS CONTROLLER, PBGA364 |
| SII3512ECTU128 | PCI BUS CONTROLLER, PQFP128 |
| SII3531ACNU | PCI BUS CONTROLLER, QCC48 |
| SIO10N268-NU | MULTIFUNCTION PERIPHERAL, PQFP128 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SII3114CTU | 制造商:Silicon Image Inc 功能描述:PCI to Serial ATA Controller 176-Pin TQFP 制造商:SILICON 功能描述: |
| SII3124A | 制造商:SILICONIMAGE 制造商全稱(chēng):SILICONIMAGE 功能描述:PCI-X to Serial ATA Controller |
| SII3124ACBHU | 制造商:SILICONIMAGE 制造商全稱(chēng):SILICONIMAGE 功能描述:PCI-X to Serial ATA Controller |
| SII3132 | 制造商:SILICONIMAGE 制造商全稱(chēng):SILICONIMAGE 功能描述:PCI Express to 2-Port Serial ATA II Host Controller |
| SII3132CNU | 制造商:Silicon Image Inc 功能描述:PCI Express to Serial ATA Controller 88-Pin QFN |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。